Test-Delivery Optimization in Manycore SOCs

We present two test-data delivery optimization algorithms for system-on-chip (SOC) designs with hundreds of cores, where a network-on-chip (NOC) is used as the interconnection fabric. We first present an e ective algorithm based on a subsetsum formulation to solve the test-delivery problem in NOCs with arbitrary topology that use dedicated routing. We further propose an algorithm for the important class of NOCs with grid topology and XY routing. The proposed algorithm is the first to co-optimize the number of access points, access-point locations, pin distribution to access points, and assignment of cores to access points for optimal test resource utilization of such NOCs. Testtime minimization is modeled as an NOC partitioning problem and solved with dynamic programming in polynomial time. Both the proposed methods yield high-quality results and are scalable to large SOCs with many cores. We present results on synthetic grid topology NOC-based SOCs constructed using cores from the ITC’02 benchmark, and demonstrate the scalability of our approach for two SOCs of the future, one with nearly 1,000 cores and the other with 1,600 cores. Test scheduling under power constraints is also incorporated in the optimization framework

An Automated Design-flow for FPGA-based Sequential Simulation

In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.\u

Cost Model-Driven Test Resource Partitioning for SoCs

The increasing complexity of modern SoCs and quality expectations are making the cost of test represent an significant fraction of the manufacturing cost. The main factors contributing to the cost of test are the required number of tester pins, the test application time, the tester memory requirements and the area overhead required by the test resources. These factors contribute with different weights, depending on the cost model of each product. Several methods have been proposed to optimize each of these factors, however none of them allows an objective function derived from the actual cost model of each product. In this paper, we propose a cost model-driven test resource allocation and scheduling method that minimizes the cost of test

A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems

Recent technological advances have greatly improved the performance and features of embedded systems. With the number of just mobile devices now reaching nearly equal to the population of earth, embedded systems have truly become ubiquitous. These trends, however, have also made the task of managing their power consumption extremely challenging. In recent years, several techniques have been proposed to address this issue. In this paper, we survey the techniques for managing power consumption of embedded systems. We discuss the need of power management and provide a classification of the techniques on several important parameters to highlight their similarities and differences. This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded systems of tomorrow

Self-partitioning SlipChip for slip-induced droplet formation and human papillomavirus viral load quantification with digital LAMP

Human papillomavirus (HPV) is one of the most common sexually transmitted infections worldwide, and persistent HPV infection can cause warts and even cancer. Nucleic acid analysis of HPV viral DNA can be very informative for the diagnosis and monitoring of HPV. Digital nucleic acid analysis, such as digital PCR and digital isothermal amplification, can provide sensitive detection and precise quantification of target nucleic acids, and its utility has been demonstrated in many biological research and medical diagnostic applications. A variety of methods have been developed for the generation of a large number of individual reaction partitions, a key requirement for digital nucleic acid analysis. However, an easily assembled and operated device for robust droplet formation without preprocessing devices, auxiliary instrumentation or control systems is still highly desired. In this paper, we present a self-partitioning SlipChip (sp-SlipChip) microfluidic device for the slip-induced generation of droplets to perform digital loop-mediated isothermal amplification (LAMP) for the detection and quantification of HPV DNA. In contrast to traditional SlipChip methods, which require the precise alignment of microfeatures, this sp-SlipChip utilized a design of “chain-of-pearls” continuous microfluidic channel that is independent of the overlapping of microfeatures on different plates to establish the fluidic path for reagent loading. Initiated by a simple slipping step, the aqueous solution can robustly self-partition into individual droplets by capillary pressure-driven flow. This advantage makes the sp-SlipChip very appealing for the point-of-care quantitative analysis of viral load. As a proof of concept, we performed digital LAMP on an sp-SlipChip to quantify human papillomaviruses (HPVs) 16 and 18 and tested this method with fifteen anonymous clinical samples

Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel

High-level synthesis (HLS) allows hardware designers to think algorithmically and not worry about low-level, cycle-by-cycle details. This provides the ability to quickly explore the architectural design space and tradeoffs between resource utilization and performance. Unfortunately, security evaluation is not a standard part of the HLS design flow. In this article, we aim to understand the effects of memory-based HLS optimizations on power side-channel leakage. We use Xilinx Vivado HLS to develop different cryptographic cores, implement them on a Spartan-6 FPGA, and collect power traces. We evaluate the designs with respect to resource utilization, performance, and information leakage through power consumption. We have two important observations and contributions. First, the choice of resource optimization directive results in different levels of side-channel vulnerabilities. Second, the partitioning optimization directive can greatly compromise the hardware cryptographic system through power side-channel leakage due to the deployment of memory control logic. We describe an evaluation procedure for power side-channel leakage and use it to make best-effort recommendations about how to design more secure architectures in the cryptographic domain