Advances in solid state switchgear technology for large space power systems

High voltage solid state remote power controllers (RPC's) and the required semiconductor power switches to provide baseline technology for large, high power distribution systems in the space station, all electric airplane and other advanced aerospace applications were developed. The RPC's were developed for dc voltages from 28 to 1200 V and ac voltages of 115, 230, and 440 V at frequencies of 400 Hz to 20 kHz. The benefits and operation of solid state RPC's and highlights of several developments to bring the RPC to technology readiness for future aerospace needs are examined. The 28 V dc Space Shuttle units, three RPC types at 120 V dc, two at 270/300 V dc, two at 230 V ac and several high power RPC models at voltages up to 1200 V dc with current ratings up to 100 A are reviewed. New technology programs to develop a new family of (DI)2 semiconductor switches and 20 kHz, 440 V ac RPC's are described

Ultra wideband communication link

Ultra-wideband communication (UWB) has been a topic of extensive research in recent years especially for its short-range communication and indoor applications. The preliminary objective of the project was to develop a description and understanding of the basic components of the communication link at microwave frequencies in order to achieve the primary objective of establishing a communication setup at a bandwidth of 2.5 GHz for testing Ultra Wideband (UWB) antennas. This was achieved with the aid of commercially available optical system which was modified for the purpose. Beginning with the generation of baseband narrow pulses with energy spanning over a broad frequency range, through multiplexing of different parallel channels carrying these pulses into a single stream, to finally capturing the received signal to understand the effect of the communication link formed; all provided basis for identifying the issues and possible solutions to establishing a reliable communication link at UWB frequency

On the nature and effect of power distribution noise in CMOS digital integrated circuits

The thesis reports on the development of a novel simulation method aimed at modelling power distribution noise generated in digital CMOS integrated circuits. The simulation method has resulted in new information concerning: 1. The magnitude and nature of the power distribution noise and its dependence on the performance and electrical characteristics of the packaged integrated circuit. Emphasis is laid on the effects of resistive, capacitative and inductive elements associated with the packaged circuit. 2. Power distribution noise associated with a generic systolic array circuit comprising 1,020,000 transistors, of which 510,000 are synchronously active. The circuit is configured as a linear array which, if fabricated using two-micron bulk CMOS technology, would be over eight centimetres long and three millimetres wide. In principle, the array will perform 1.5 x 10 to the power of 11 operations per second. 3. Power distribution noise associated with a non-array-based signal processor which, if fabricated in 2-micron bulk CMOS technology, would occupy 6.7 sq. cm. The circuit contains about 900,000 transistors, of which 600,000 are functional and about 300,000 are used for yield enhancement. The processor uses the RADIX-2 algorithm and is designed to achieve 2 x 10 to the power of 8 floating point operations per second. 4. The extent to which power distribution noise limits the level of integration and/ or performance of such circuits using standard and non-standard fabrication and packaging technology. 5. The extent to which the predicted power distribution noise levels affect circuit susceptibility to transient latch-up and electromigration. It concludes the nature of CMOS digital integrated circuit power distribution noise and recommends ways in which it may be minimised. It outlines an approach aimed at mechanising the developed simulation methodology so that the performance of power distribution networks may more routinely be assessed. Finally. it questions the long term suitability of mainly digital techniques for signal processing

Microprocessor Solder Bump Bridging Defects Screening Strategy In Manufacturing Test Flow

Solder bump bridging (SBB) is a type microprocessor packaging defects in Flip-Chip or C4 interconnection layer. The presence of micro conductive contaminate particle in die-package layer which causes bridging between two or more adjacent solder bump. These contaminate particles are mainly comes from solder bump fraction result from deficient packaging process. Today semiconductor manufacturing test flow is still imperfect to completely screen or detect the SBB defect. As bounce back, the test holes contributes to the defect per million (DPM) of the product. In this research, the test holes of SBB defect in High Volume Manufacturing (HVM) will be defined. Meanwhile, SBB defect characterization will be studied where the electrical behavioural of baby bumps is explained. In the final part of the study, an effective SBB screening test at Burn In is developed to minimizing test holes. From the research finding, un-bridging of SBB occurs at extreme high current of 4.5 A where the baby bump burnt and partial unbridged. This unbridged state are unstable and lacking in term of reliability. However, the SBB un-bridging only impacted on Type B SBB defect where baby bump bridging power bump with ground bump. Lastly, the SBB screening test at Burn In stage is developed as part of this research. In conclusion, the proposed test has the potential in minimizing HVM SBB defect test holes by improving SBB defect fault coverage

Locally-Stable Macromodels of Integrated Digital Devices for Multimedia Applications

This paper addresses the development of accurate and efficient behavioral models of digital integrated circuits for the assessment of high-speed systems. Device models are based on suitable parametric expressions estimated from port transient responses and are effective at system level, where the quality of functional signals and the impact of supply noise need to be simulated. A potential limitation of some state-of-the-art modeling techniques resides in hidden instabilities manifesting themselves in the use of models, without being evident in the building phase of the same models. This contribution compares three recently-proposed model structures, and selects the local-linear state-space modeling technique as an optimal candidate for the signal integrity assessment of data links. In fact, this technique combines a simple verification of the local stability of models with a limited model size and an easy implementation in commercial simulation tools. An application of the proposed methodology to a real problem involving commercial devices and a data-link of a wireless device demonstrates the validity of this approac

NASA Space Engineering Research Center for VLSI systems design

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design

Test and Diagnosis of Integrated Circuits

The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users, the manufacturing process is becoming finer and denser, making chips more prone to defects.The work presented in the HDR manuscript addresses the challenges of test and diagnosis of integrated circuits. It covers:- Power aware test;- Test of Low Power Devices;- Fault Diagnosis of digital circuits