BRAHMS: Novel middleware for integrated systems computation

Biological computational modellers are becoming increasingly interested in building large, eclectic models, including components on many different computational substrates, both biological and non-biological. At the same time, the rise of the philosophy of embodied modelling is generating a need to deploy biological models as controllers for robots in real-world environments. Finally, robotics engineers are beginning to find value in seconding biomimetic control strategies for use on practical robots. Together with the ubiquitous desire to make good on past software development effort, these trends are throwing up new challenges of intellectual and technological integration (for example across scales, across disciplines, and even across time) - challenges that are unmet by existing software frameworks. Here, we outline these challenges in detail, and go on to describe a newly developed software framework, BRAHMS. that meets them. BRAHMS is a tool for integrating computational process modules into a viable, computable system: its generality and flexibility facilitate integration across barriers, such as those described above, in a coherent and effective way. We go on to describe several cases where BRAHMS has been successfully deployed in practical situations. We also show excellent performance in comparison with a monolithic development approach. Additional benefits of developing in the framework include source code self-documentation, automatic coarse-grained parallelisation, cross-language integration, data logging, performance monitoring, and will include dynamic load-balancing and 'pause and continue' execution. BRAHMS is built on the nascent, and similarly general purpose, model markup language, SystemML. This will, in future, also facilitate repeatability and accountability (same answers ten years from now), transparent automatic software distribution, and interfacing with other SystemML tools. (C) 2009 Elsevier Ltd. All rights reserved

Advanced flight computer. Special study

This report documents a special study to define a 32-bit radiation hardened, SEU tolerant flight computer architecture, and to investigate current or near-term technologies and development efforts that contribute to the Advanced Flight Computer (AFC) design and development. An AFC processing node architecture is defined. Each node may consist of a multi-chip processor as needed. The modular, building block approach uses VLSI technology and packaging methods that demonstrate a feasible AFC module in 1998 that meets that AFC goals. The defined architecture and approach demonstrate a clear low-risk, low-cost path to the 1998 production goal, with intermediate prototypes in 1996

Digital signal processor fundamentals and system design

Digital Signal Processors (DSPs) have been used in accelerator systems for more than fifteen years and have largely contributed to the evolution towards digital technology of many accelerator systems, such as machine protection, diagnostics and control of beams, power supply and motors. This paper aims at familiarising the reader with DSP fundamentals, namely DSP characteristics and processing development. Several DSP examples are given, in particular on Texas Instruments DSPs, as they are used in the DSP laboratory companion of the lectures this paper is based upon. The typical system design flow is described; common difficulties, problems and choices faced by DSP developers are outlined; and hints are given on the best solution

HETE Satellite Processing System

The HETE (High Energy Transient Experiment) satellite is a joint project between MIT\u27s Center for Space Research and AeroAstro. The primary goal of the High Energy Transient Experiment is to determine the origin and nature of cosmic gamma-ray bursts. The objectives include the simultaneous broad band observation of energetic, transient astrophysical sources in the UV, x-ray and gamma-ray energy ranges, and the precise location and identification of cosmic gamma-ray burst sources. A continuous slow data rate down link of major events is to be broadcast to 20 receive-only ground stations, allowing other astrophysical assets to observe events detected by HETE. AeroAstro is building the HETE spacecraft bus for MIT and is responsible for the development, manufacture test, and integration of the spacecraft bus. and spacecraft bus hardware / payload hardware integration. AeroAstro will also provide the complete ground segment consisting of 2 full duplex ground stations and approximately 20 receive-only ground stations. This paper presents a summary of the HETE satellite data processing system designed and manufactured by AeroAstro. The data handling system which is built around a combination of the INMOS Transputer and a Motorola DSP56001 processor which is also used to manage most of the other spacecraft functions such as attitude control and power management. Payload processors, memory system and spacecraft processor are integrated in the spacecraft central electronics box, and share a common back plane

Development of a TIM-compliant TMS320C6x DSP module

The development of a Texas instruments Module (TIM) compliant Digital SignalProcessor (DSP) module, using the Texas Instruments TMS320C6201 (C6201) DSP, is presented. Currently, DSP modules based on the Texas Instruments TMS320C4x(C4x) family of DSPs are widely used for message passing multiprocessing DSPapplications such as real-time processing of data and image processing. The Interconnection of the TIM-compliant C4x DSP modules is accomplished using motherboards based on standard bus types, such as VME or PCI, and communication ports (comm ports) built into the C4x DSP. The purpose of the work described in this thesis was to provide a TIM-compliant DSP module with the improved computational performance of the C6x family of DSPs, which would also be compatible with theexisting VME or PCI bus motherboards.One drawback to using the C6201 DSPs in this application is the lack of C4xtype communication ports (comm ports) in these new DSPs. In order for the C6201 TIM to be compatible with the existing motherboards, it must provide C4x- compatible commport functionality. An FPGA was used to convert the C6x host port into multiple C4x compatible communication ports and to provide the potential for future co-processinghardware.The major effort of this development was the designing, building and testing of the C6x module hardware and the C4x-compatible comm port interface implemented in FPGA. The first phase of this design involved the hardware architecture; this consisted of the selection of components needed to fulfill the design constraints, and the design of the module printed circuit board (PCB). The major components of this DSPmodule consist of theC6201 DSP. The external ai memory devices, and an Altera PF10 10pA Field Programmable Gate Array (FPGA). The memory devices include 4MB of SDRAM. 256kB of SBSRAM, and a 512kB Flash ROM for storing boot code. The Second phase of this design dealt with the host port to comm port conversion hardware implemented in the FPGA. The C6x host port was used to exchange data and control information with the FPGA. This hardware was developed in the VHDL hardware description language and graphic design files using Altera MAX+PLUS II software.The C6201 DSP module has been built and tested. The board successfully executed both read and write transfers with another motherboard using the C4x compatible communication port interface. The data exchange was across a 2.5\u27 ribbon cable at an average read transfer data rate of 7.18 Mbytes/S and an average write transfer data rate of 5.15 Mbytes/S