Obtaining performance and programmability using reconfigurable hardware for media processing

Thesis (Ph. D.)--Massachusetts Institute of Technology, School of Architecture and Planning, Program in Media Arts and Sciences, 2002.Includes bibliographical references (p. 127-132).An imperative requirement in the design of a reconfigurable computing system or in the development of a new application on such a system is performance gains. However, such developments suffer from long-and-difficult programming process, hard-to-predict performance gains, and limited scope of applications. To address these problems, we need to understand reconfigurable hardware's capabilities and limitations, its performance advantages and disadvantages, re-think reconfigurable system architectures, and develop new tools to explore its utility. We begin by examining performance contributors at the system level. We identify those from general-purpose and those from dedicated components. We propose an architecture by integrating reconfigurable hardware within the general-purpose framework. This is to avoid and minimize dedicated hardware and organization for programmability. We analyze reconfigurable logic architectures and their performance limitations. This analysis leads to a theory that reconfigurable logic can never be clocked faster than a fixed-logic design based on the same fabrication technology. Though highly unpredictable, we can obtain a quick upper bound estimate on the clock speed based on a few parameters. We also analyze microprocessor architectures and establish an analytical performance model. We use this model to estimate performance bounds using very little information on task properties. These bounds help us to detect potential memory-bound tasks. For a compute-bound task, we compare its performance upper bound with the upper bound on reconfigurable clock speed to further rule out unlikely speedup candidates.(cont.) These performance estimates require very few parameters, and can be quickly obtained without writing software or hardware codes. They can be integrated with design tools as front end tools to explore speedup opportunities without costly trials. We believe this will broaden the applicability of reconfigurable computing.by Ling-Pei Kung.Ph.D

Proceedings of the First NASA Formal Methods Symposium

Topics covered include: Model Checking - My 27-Year Quest to Overcome the State Explosion Problem; Applying Formal Methods to NASA Projects: Transition from Research to Practice; TLA+: Whence, Wherefore, and Whither; Formal Methods Applications in Air Transportation; Theorem Proving in Intel Hardware Design; Building a Formal Model of a Human-Interactive System: Insights into the Integration of Formal Methods and Human Factors Engineering; Model Checking for Autonomic Systems Specified with ASSL; A Game-Theoretic Approach to Branching Time Abstract-Check-Refine Process; Software Model Checking Without Source Code; Generalized Abstract Symbolic Summaries; A Comparative Study of Randomized Constraint Solvers for Random-Symbolic Testing; Component-Oriented Behavior Extraction for Autonomic System Design; Automated Verification of Design Patterns with LePUS3; A Module Language for Typing by Contracts; From Goal-Oriented Requirements to Event-B Specifications; Introduction of Virtualization Technology to Multi-Process Model Checking; Comparing Techniques for Certified Static Analysis; Towards a Framework for Generating Tests to Satisfy Complex Code Coverage in Java Pathfinder; jFuzz: A Concolic Whitebox Fuzzer for Java; Machine-Checkable Timed CSP; Stochastic Formal Correctness of Numerical Algorithms; Deductive Verification of Cryptographic Software; Coloured Petri Net Refinement Specification and Correctness Proof with Coq; Modeling Guidelines for Code Generation in the Railway Signaling Context; Tactical Synthesis Of Efficient Global Search Algorithms; Towards Co-Engineering Communicating Autonomous Cyber-Physical Systems; and Formal Methods for Automated Diagnosis of Autosub 6000

An SOPC Based Image Processing System

Recent advances in semiconductor technology have made it possible to integrate an entire system including processors, memory and other system units into a single programmable chip - FPGA, these configurations are called 'System-on-aProgrammable- Chip' (SOPC). SOPCs have the advantage that they can be designed quicker than existing technologies and are cheap to produce for low volume «10,000) applications. Also, SOPCs are of great benefit as they offer compact and flexible system designs due to their reconfigurable nature and high integration of features. One processor intensive application, which is ideal for SOPC technology, is that of image processing where there is a repeated application of operations on the 2D data. This research investigated the use of SOPC technology for image processing by developing a modular system capable ofreal-time video acquisition, processing and display. An sope Based Image Processing System Abstract Abstract This system is comprised of a CameraLink CMOS camera with a custom designed camera interface card for video acquisition, a VGA mode CRT monitor with a Lancelot VGA card for video display, an industrial SDRAM device for video data buffering, and an Altera Apex 20K FPGA for evaluating the SOPC design. Four custom designed IP components have been developed and integrated with other Altera provided standard IP components to drive all off-chip peripherals and perform the required video functions such as processing the images. These custom designed IPs are the video capture controller, video display controller, video memory controller and Cache. A Nios processor was chosen to perform the actual image processing, and the whole system was developed on the Altera Nios development board. In order to solve the complex on-chip data communication, while not degrading the transferring speed of largeamounts of video data, an effective solution called Simultaneously Multi-Mastering Avalon Streaming Transfer with Peripheral-Controlled Waitrequest was raised. Rather than using the software approach to initialise DMA-like transfers, this solution takes advantage of the FPGA hardware resource to perform bus arbitration and hence increases the system efficiency. The system produced is an alternative to conventional desktop-based, i.e. a visionbased closed loop process control system for weiding, or microprocessor-based vision systems. September 2007 FanWu Supplied by The British Library - 'The world's knowledge