2,517 research outputs found

    An intelligent, multi-transducer signal conditioning design for manufacturing applications

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    This paper describes a flexible, intelligent, high bandwidth, signal conditioning reference design and implementation, which is suitable for a wide range of force and displacement transducers in manufacturing applications. The flexibility inherent in the design has allowed more than 10 specialised transducer conditioning boards to be replaced by this single design, in a range of bespoke mechanical test equipment manufactured by the authors. The board is able to automatically reconfigure itself for a wide range of transducers and calibrate and balance the transducer. The range of transducers includes LVDT, AC/DC strain gauge and inductive bridges, and a range of standard industrial voltage current interface transducers. Further, with a minor lowcost addition to the transducer connector, the board is able to recognise the type of transducer, reconfigure itself and store the calibration data within the transducer, thereafter allowing a plugand-play operation as transducers are changed. The paper provides an example of the operation in typical manufacturing test application and illustrates the stability and noise performance of the design

    Design of On-Chip Self-Testing Signature Register

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    Over the last few years, scan test has turn out to be too expensive to implement for industry standard designs due to increasing test data volume and test time. The test cost of a chip is mainly governed by the resource utilization of Automatic Test Equipment (ATE). Also, it directly depends upon test time that includes time required to load test program, to apply test vectors and to analyze generated test response of the chip. An issue of test time and data volume is increasingly appealing designers to use on-chip test data compactors, either on input side or output side or both. Such techniques significantly address the former issues but have little hold over increasing number of input-outputs under test mode. Further, test pins on DUT are increasing over the generations. Thus, scan channels on test floor are falling short in number for placement of such ICs. To address issues discussed above, we introduce an on-chip self-testing signature register. It comprises a response compactor and a comparator. The compactor compacts large chunk of response data to a small test signature whereas the comparator compares this test signature with desired one. The overall test result for the design is generated on single output pin. Being no storage of test response is demanded, the considerable reduction in ATE memory can be observed. Also, with only single pin to be monitored for test result, the number of tester channels and compare edges on ATE side significantly reduce at the end of the test. This cuts down maintenance and usage cost of test floor and increases its life time. Furthermore reduction in test pins gives scope for DFT engineers to increase number of scan chains so as to further reduce test time

    Efficient Path Delay Test Generation with Boolean Satisfiability

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    This dissertation focuses on improving the accuracy and efficiency of path delay test generation using a Boolean satisfiability (SAT) solver. As part of this research, one of the most commonly used SAT solvers, MiniSat, was integrated into the path delay test generator CodGen. A mixed structural-functional approach was implemented in CodGen where longest paths were detected using the K Longest Path Per Gate (KLPG) algorithm and path justification and dynamic compaction were handled with the SAT solver. Advanced techniques were implemented in CodGen to further speed up the performance of SAT based path delay test generation using the knowledge of the circuit structure. SAT solvers are inherently circuit structure unaware, and significant speedup can be availed if structure information of the circuit is provided to the SAT solver. The advanced techniques explored include: Dynamic SAT Solving (DSS), Circuit Observability Don’t Care (Cir-ODC), SAT based static learning, dynamic learnt clause management and Approximate Observability Don’t Care (ACODC). Both ISCAS 89 and ITC 99 benchmarks as well as industrial circuits were used to demonstrate that the performance of CodGen was significantly improved with MiniSat and the use of circuit structure

    Perpetual Pavement Instrumentation for the Marquette Interchange Project-Phase 1

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    This report provides details on the design, installation and monitoring of a pavement instrumentation system for the analysis of load-induced stresses and strains within a perpetual HMA pavement system. The HMA pavement was constructed as part of an urban highway improvement project in the City of Milwaukee, Wisconsin. The outer wheel path of the outside lane was instrumented with asphalt strain sensors, base and subgrade pressure sensors, subgrade moisture and temperature sensors, HMA layer temperature sensors, traffic wander strips and a weigh in motion system. Environmental sensors for air temperature, wind speed and solar radiation are also included. The system captures the pavement response from each axle loading and transmits the data through a wireless link to a resident database at Marquette University. The collected data will be used to estimate the fatigue life of the perpetual HMA pavement and to modify, as necessary, pavement design procedures used within the State of Wisconsin

    Marquette Interchange Phase I Final Report

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    This report provides details on the design, installation and monitoring of a pavement instrumentation system for the analysis of load-induced stresses and strains within a perpetual HMA pavement system. The HMA pavement was constructed as part of an urban highway improvement project in the City of Milwaukee, Wisconsin. The outer wheel path of the outside lane was instrumented with asphalt strain sensors, base and subgrade pressure sensors, subgrade moisture and temperature sensors, HMA layer temperature sensors, traffic wander strips and a weigh in motion system. Environmental sensors for air temperature, wind speed and solar radiation are also included. The system captures the pavement response from each axle loading and transmits the data through a wireless link to a resident database at Marquette University. The collected data will be used to estimate the fatigue life of the perpetual HMA pavement and to modify, as necessary, pavement design procedures used within the State of Wisconsin

    A Lightweight N-Cover Algorithm For Diagnostic Fail Data Minimization

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    The increasing design complexity of modern ICs has made it extremely difficult and expensive to test them comprehensively. As the transistor count and density of circuits increase, a large volume of fail data is collected by the tester for a single failing IC. The diagnosis procedure analyzes this fail data to give valuable information about the possible defects that may have caused the circuit to fail. However, without any feedback from the diagnosis procedure, the tester may often collect fail data which is potentially not useful for identifying the defects in the failing circuit. This not only consumes tester memory but also increases tester data logging time and diagnosis run time. In this work, we present an algorithm to minimize the amount of fail data used for high quality diagnosis of the failing ICs. The developed algorithm analyzes outputs at which the tests failed and determines which failing tests can be eliminated from the fail data without compromising diagnosis accuracy. The proposed algorithm is used as a preprocessing step between the tester data logs and the diagnosis procedure. The performance of the algorithm was evaluated using fail data from industry manufactured ICs. Experiments demonstrate that on average, 43% of fail data was eliminated by our algorithm while maintaining an average diagnosis accuracy of 93%. With this reduction in fail data, the diagnosis speed was also increased by 46%

    Multiprocessing techniques for unmanned multifunctional satellites Final report,

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    Simulation of on-board multiprocessor for long lived unmanned space satellite contro

    High Quality Test Generation Targeting Power Supply Noise

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    Delay test is an essential structural manufacturing test used to determine the maximal frequency at which a chip can run without incurring any functional failures. The central unsolved challenge is achieving high delay correlation with the functional test, which is dominated by power supply noise (PSN). Differences in PSN between functional and structural tests can lead to differences in chip operating frequencies of 30% or more. Pseudo functional test (PFT), based on a multiple-cycle clocking scheme, has better PSN correlation with functional test compared with traditional two-cycle at-speed test. However, PFT is vulnerable to under-testing when applied to delay test. This work aims to generate high quality PFT patterns, achieving high PSN correlation with functional test. First, a simulation-based don’t-care filling algorithm, Bit-Flip, is proposed to improve the PSN for PFT. It relies on randomly flipping a group of bits in the test pattern to explore the search space and find patterns that stress the circuits with the worst-case, but close to functional PSN. Experimental results on un-compacted patterns show Bit-Flip is able to improve PSN as much as 38.7% compared with the best random fill. Second, techniques are developed to improve the efficiency of Bit-Flip. A set of partial patterns, which sensitize transitions on critical cells, are pre-computed and later used to guide the selection of bits to flip. Combining random and deterministic flipping, we achieve similar PSN control as Bit-Flip but with much less simulation time. Third, we address the problem of automatic test pattern generation for extracting circuit timing sensitivity to power supply noise during post-silicon validation. A layout-aware path selection algorithm selects long paths to fully span the power delivery network. The selected patterns are intelligently filled to bring the PSN to a desired level. These patterns can be used to understand timing sensitivity in post-silicon validation by repeatedly applying the path delay test while sweeping the PSN experienced by the path from low to high. Finally, the impacts of compression on power supply noise control are studied. Illinois Scan and embedded deterministic test (EDT) patterns are generated. Then Bit-Flip is extended to incorporate the compression constraints and applied to compressible patterns. The experimental results show that EDT lowers the maximal PSN by 24.15% and Illinois Scan lowers it by 2.77% on un-compacted patterns
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