Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip

A micropower centroiding vision processor

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A Readout System for the STAR Time Projection Chamber

We describe the readout electronics for the STAR Time Projection Chamber. The system is made up of 136,608 channels of waveform digitizer, each sampling 512 time samples at 6-12 Mega-samples per second. The noise level is about 1000 electrons, and the dynamic range is 800:1, allowing for good energy loss ($dE/dx$) measurement for particles with energy losses up to 40 times minimum ionizing. The system is functioning well, with more than 99% of the channels working within specifications.Comment: 22 pages + 8 separate figures; 2 figures are .jpg photos to appear in Nuclear Instruments and Method

Data Cache-Energy and Throughput Models: Design Exploration for Embedded Processors

Most modern 16-bit and 32-bit embedded processors contain cache memories to further increase instruction throughput of the device. Embedded processors that contain cache memories open an opportunity for the low-power research community to model the impact of cache energy consumption and throughput gains. For optimal cache memory configuration mathematical models have been proposed in the past. Most of these models are complex enough to be adapted for modern applications like run-time cache reconfiguration. This paper improves and validates previously proposed energy and throughput models for a data cache, which could be used for overhead analysis for various cache types with relatively small amount of inputs. These models analyze the energy and throughput of a data cache on an application basis, thus providing the hardware and software designer with the feedback vital to tune the cache or application for a given energy budget. The models are suitable for use at design time in the cache optimization process for embedded processors considering time and energy overhead or could be employed at runtime for reconfigurable architectures

CUSTARD (Cranfield University Space Technology Advanced Research Demonstrator) - A Micro-System Technology Demonstrator Nanosatellite. Summary of the Group Design Project MSc in Astronautics and Space Engineering. 1999-2000, Cranfield University

CUSTARD (Cranfield University Space Technology And Research Demonstrator) was the group design project for students of the MSc in Astronautics and Space Engineering for the Academic Year 1999/2000 at Cranfield University. The project involved the initial design of a nanosatellite to be used as a technology demonstrator for microsystem technology (MST) in space. The students worked together as one group (organised into several subgroups, e.g. system, mechanical), with each student responsible for a set of work packages. The nanosatellite designed had a mass of 4 kg, lifetime of 3 months in low Earth orbit, coarse 3-axis attitude control (no orbit control), and was capable of carrying up to 1 kg of payload. The electrical power available was 18 W (peak). Assuming a single X-band ground station at RAL (UK), a data rate of up to 1 M bit s-1 for about 3000 s per day is possible. The payloads proposed are a microgravity laboratory and a formation flying experiment. The report summarises the results of the project and includes executive summaries from all team members. Further information and summaries of the full reports are available from the College of Aeronautics, Cranfield University