Alternative Lithographic Methods for Variable Aspect Ratio Vias

The foundation of semiconductor industry has historically been driven by scaling. Device size reduction is enabled by increased pattern density, enhancing functionality and effectively reducing cost per chip. Aggressive reductions in memory cell size have resulted in systems with diminishing area between parallel bit/word lines. This affords an even greater challenge in the patterning of contact level features that are inherently difficult to resolve because of their relatively small area, a product of their two domain critical dimension image. To accommodate these trends there has been a shift toward the implementation of elliptical contact features. This empowers designers to maximize the use of free space between bit/word lines and gate stacks while preserving contact area; effectively reducing the minor via axis dimension while maintaining a patternable threshold in increasingly dense circuitry. It is therefore critical to provide methods that enhance the resolving capacity of varying aspect ratio vias for implementation in electronic design systems. This work separately investigates two unique, non-traditional lithographic techniques in the integration of an optical vortex mask as well as a polymer assembly system as means to augment ellipticity while facilitating contact feature scaling. This document affords a fundamental overview of imaging theory, details previous literature as to the technological trends enabling the resolving of contact features and demonstrates simulated & empirical evidence that the described methods have great potential to extend the resolution of variable aspect ratio vias using lithographic technologies

Design automation algorithms for advanced lithography

In circuit manufacturing, as the technology nodes keep shrinking, conventional 193 nm immersion lithography (193i) has reached its printability limit. To continue the scaling with Moore's law, different kinds of advanced lithography have been proposed, such as multiple patterning lithography (MPL), extreme ultraviolet (EUV), electron beam lithography (EBL) and directed self-assembly (DSA). While these new technologies create enormous opportunities, they also pose great design challenges due to their unique process characteristics and stringent constraints. In order to smoothly adopt these advanced lithography technologies in integrated circuit (IC) fabrication, effective electronic design automation (EDA) algorithms must be designed and integrated into computer-aided design (CAD) tools to address the underlying design constraints and help the circuit designer to better facilitate the lithography process. In this thesis, we focus on algorithmic design and efficient implementation of EDA algorithm for advanced lithography, including directed self-assembly (DSA) and self-aligned double patterning (SADP), to conquer the physical challenges and improve the manufacturing yield. The first advanced lithography technology we explore is self-aligned double patterning (SADP). SADP has the significant advantage over traditional litho-etch-litho-etch (LELE) double patterning in its ability to eliminate overlay, making it a preferable DPL choice for the 14 nm technology node. As in any DPL technology, layout decomposition is the key problem. While the layout decomposition problem for LELE DPL has been well studied in the literature, only a few attempts have been made for the SADP layout decomposition problem. This thesis studies the SADP decomposition problem in different scenarios. SADP has been successfully deployed in 1D patterns and has several applications; however, applying it to 2D patterns turns out to be much more difficult. All previous exact algorithms were based on computationally expensive methods such as SAT or ILP. Other previous algorithms were heuristics without a guarantee that an overlay-free solution can be found even if one exists. The SADP decomposition problem on general 2D layout is proven to be NP-complete. However, we show that if we restrict the overlay, the problem is polynomial-time solvable, and present an exact algorithm to determine if a given 2D layout has a no-overlay SADP decomposition. When designing the layout decomposition algorithms, it is usually useful to take the layout structure into consideration. As most of the current IC layouts adopt a row-based standard cell design style, we can take advantage of its characteristics and design more efficient algorithms compared to the algorithms for general 2D patterns. In particular, the fixed widths of standard cells and power tracks on top and bottom of cells suggest that improvements can be made over the algorithms for general decomposition problem. We present a shortest-path based polynomial time SADP decomposition algorithm for row-based standard cell layout that efficiently finds decompositions with minimum overlay violations. Our proposed algorithm takes advantage of the fixed width of the cells and the alternating power tracks between the rows to limit the possible decompositions and thus achieve high efficiency. The next advanced lithography technology we discuss in the thesis is directed self-assembly (DSA). Block copolymer directed self-assembly (DSA) is a promising technique for patterning contact holes and vias in 7 nm technology nodes. To pattern contacts/vias with DSA, guiding templates are usually printed first with conventional lithography (193i) that has a coarser pitch resolution. Contact holes are then patterned with DSA process. The guiding templates play the role of defining the DSA patterns, which have a finer resolution than the templates. As a result, different patterns can be obtained through controlling the templates. It is shown that DSA lithography is very promising in patterning contacts/vias in 7 nm technology node. However, to utilize DSA for full-chip manufacturing, EDA for DSA must be fully explored because EDA is the key enabler for manufacturing, and the EDA research for DSA is still lagging behind. To pattern the contact layer with DSA, we must ensure that all the contacts in the layout require only feasible DSA templates. Nevertheless, the original layout may not be designed in a DSA-friendly way. However, even with an optimized library, infeasible templates may be introduced after the physical design phase. We propose a simulated-annealing (SA) based scheme to perform full-chip level contact layer optimization. According to the experimental results, the DSA conflicts in the contact layer are reduced by close to 90% on average after applying the proposed optimization algorithm. It is a current trend that industry is transiting from the random 2D designs to highly regular 1D gridded designs for sub-20 nm nodes and fabricating circuit designs with print-cut technology. In this process, the randomly distributed cuts may be too dense to be printed by single patterning lithography. DSA has proven its success in contact hole patterning, and can be easily expanded to cut printing for 1D gridded designs. Nevertheless, the irregular distribution of cuts still presents a great challenge for DSA, as the self-assembly process usually forms regular patterns. As a result, the cut layer must be optimized for the DSA process. To address the above problem, we propose an efficient algorithm to optimize cut layers without hurting the original circuit logic. Our work utilizes a technique called `line-end extension' to move the cuts and extend the functional wires without changing the original functionality of the circuit. Consequently, the cuts can be redistributed and grouped into valid DSA templates. Multiple patterning lithography has been widely adopted for today's circuit manufacturing. However, increasing the number of masks will make the manufacturing process more expensive. By incorporating DSA into the multiple patterning process, it is possible to reduce the number of masks and achieve a cost-effective solution. We study the decomposition problem for the contact layer in row-based standard cell layout with DSA-MP complementary lithography. We explore several heuristic-based approaches, and propose an algorithm that decomposes a standard cell row optimally in polynomial-time. Our experiments show that our algorithm is guaranteed to find a minimum cost solution if one exists, while the heuristic cannot or only finds a sub-optimal solution. Our results show that the DSA-MP complementary approach is very promising for the future advanced nodes. As in any lithography technique, the process variation control and proximity correction are the most important issues. As the DSA templates are patterned by conventional lithography, the patterned templates are prone to deviate from mask shapes due to process variations, which will ultimately affect the contacts after the DSA process even for the same type of template. Therefore, in order to enable the DSA technology in contact/via layer printing, it is extremely important to accurately model and detect hotspots, as well as estimate the contact pitch and locations during the verification phase. We propose a machine learning based design automation framework for DSA verification. A novel DSA model and a set of features are included. We implemented the proposed ML-based flow and performed extensive experiments on comparing the performances of learning algorithms and features. The experimental results show that our approach is much more efficient than the traditional approach, and can produce highly accurate results

Colloidal lithography for photovoltaics: An attractive route for light management

DFA/BD/7882/2020The pursuit of ever‐more efficient, reliable, and affordable solar cells has pushed the development of nano/micro‐technological solutions capable of boosting photovoltaic (PV) performance without significantly increasing costs. One of the most relevant solutions is based on light management via photonic wavelength‐sized structures, as these enable pronounced efficiency improvements by reducing reflection and by trapping the light inside the devices. Furthermore, optimized microstructured coatings allow self‐cleaning functionality via effective water repulsion, which reduces the accumulation of dust and particles that cause shading. Nevertheless, when it comes to market deployment, nano/micro‐patterning strategies can only find application in the PV industry if their integration does not require high additional costs or delays in high‐throughput solar cell manufacturing. As such, colloidal lithography (CL) is considered the preferential structuring method for PV, as it is an inexpensive and highly scalable soft‐patterning technique allowing nanoscopic precision over indefinitely large areas. Tuning specific parameters, such as the size of colloids, shape, monodispersity, and final arrangement, CL enables the production of various templates/masks for different purposes and applications. This review intends to compile several recent high‐profile works on this subject and how they can influence the future of solar electricity.publishersversionpublishe

Flexible and reusable parylene C mask technology for applications in cascade impactor air quality monitoring systems

The development of traceable new methodologies to quantify elemental air pollutants in particulate matter (PM) supports modernization of methods used in air quality monitoring networks in Europe. In the framework of the EURAMET EMPIR AEROMET II project, the combination of cascade impactor aerosol sampling and total reflection X-ray fluorescence elemental spectroscopy (TXRF) was investigated. This technique requires a traceable calibration based on reference samples. This paper describes a new, simple and effective method to produce such reference samples using flexible, reusable, and low-cost parylene C shadow masks, fabricated by photolithographic steps. These shadow masks can be used to produce reference samples that mimic the Dekati cascade impactor's deposition patterns by applying as-prepared micro stencils to 30 mm acrylic substrates and evaporating a reference material (Ti) in arrangements of thin circular dots. The highly flexible direct patterning of acrylic discs with reference material, otherwise impossible with conventional photolithography, allows multiple reusing of the same micro stencils. The aspect ratios of the dots could be repeated with an error less than 4%. A first set of standard reference samples for the 13 stages of the Dekati cascade impactor was produced and preliminary TXRF measurements of the deposited Ti masses were performed. The centricity of the deposition patterns turned out to be an important parameter for the quality of the TXRF results. The parylene mask technology for the production of reference samples turns out to be a promising new approach for the traceable calibration of TXRF spectrometers for the quantification of element concentrations in environmental aerosol samples but, due to its great versatility, it could be used for several other micropatterning applications on conventional and unconventional substrates

Development of high-resolution shadow masks using thin membranes of parylene-C for patterning microelectronic devices

In order to fabricate microelectronic devices, patterning techniques such as photolithography or shadow mask patterning must be performed. This last technique uses a physical mask to block regions on the substrate during film deposition and its resolution is determined by the thickness of the mask and the fabrication procedures. This thesis reports the fabrication of Parylene-C thin shadow masks, 3 and 5 m, and their application in single-step and multi-step patterning and, on curved surfaces. The results for single-step patterning showed the possibility of defining features with a resolution of 10 m. When multi-step patterning the maximum resolution obtained in the produced masks was 20 m for separation between features and 40 m for lines where this resolution was limited by the photolithographic masks used. For the alignment, several strategies were tested but the one that presented the best results was the use of SU-8 pillars to align different shadow masks in order to pattern microelectronic devices with 10 m of tolerance. The produced shadow masks sets for TFT patterning were only one used one time and maintained the same yield from before patterning. For fiber patterning, the obtained results are promising since it showed the possibility of patterning in a curved surface using a simpler and low-cost technique. It was possible to deposit three material layers to fabricate a capacitor. It was possible to pattern a circle of 1 mm in diameter on a fiber with 750 m of diameter. This work allowed to fabricate ultra-thin masks in Parylene producing features of high resolution and features on curved surfaces showing how this material can be used as a complement in microelectronic device fabrication