p-GaAs nanowire MESFETs with near-thermal limit gating

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical sub-threshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio $\sim 10^{5}$, on-resistance ~700 k$\Omega$, contact resistance ~30 k$\Omega$, peak transconductance 1.2 $\mu$S/$\mu$m and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates whilst leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance

A Low-power CMOS 2-PPM Demodulator for Energy Detection IR-UWB Receivers

This paper presents an integrated 2-PPM CMOS demodulator for non-coherent energy detection receivers which inherently provides analog-to-digital conversion. The device, called Bi-phase integrator, employs an open loop Gm - C integrator loaded with a switched capacitor network. The circuit has been simulated in a mixed-mode UMC 0.18mum technology and its performance figures are obtained through a mixed-signal simulation environment developed with the aid of ADVanceMS (ADMS, mentor graphics). Bit-error-rate simulations show that the circuit performance is about the same of an ideal energy detection receiver employing infinite quantization resolution. In addition, the simulations show that the circuit provides a complete offset rejection. Thanks to its low power consumption (1 mW during demodulation), its application is appealing for portable devices which aim at very low-power consumption

Low-temperature Fabrication Process for Integrated High-Aspect Ratio Metal Oxide Nanostructure Semiconductor Gas Sensors

This work presents a new low-temperature fabrication process of metal oxide nanostructures that allows high-aspect ratio zinc oxide (ZnO) and titanium dioxide (TiO2) nanowires and nanotubes to be readily integrated with microelectronic devices for sensor applications. This process relies on a new method of forming a close-packed array of self-assembled high-aspect-ratio nanopores in an anodized aluminum oxide (AAO) template in a thin (2.5 µm) aluminum film deposited on a silicon and lithium niobate substrate (LiNbO3). This technique is in sharp contrast to traditional free-standing thick film methods and the use of an integrated thin aluminum film greatly enhances the utility of such methods. We have demonstrated the method by integrating ZnO nanowires, TiO2 nanowires, and multiwall TiO2 nanotubes onto the metal gate of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and the delay line of a surface acoustic wave (SAW) device to form an integrated ChemFET (Chemical Field-Effect Transistor) and a orthogonal frequency coded (OFC) SAW gas sensor. The resulting metal oxide nanostructures of 1-1.7 µm in height and 40-100 nm in diameter offer an increase of up to 220X the surface area over a standard flat metal oxide film for sensing applications. The metal oxide nanostructures were characterized by SEM, EDX, TEM and Hall measurements to verify stoichiometry, crystal structure and electrical properties. Additionally, the electrical response of ChemFETs and OFC SAW gas sensors with ZnO nanowires, TiO2 nanowires, and multiwall TiO2 nanotubes were measured using 5-200 ppm ammonia as a target gas at room temperature (24ºC) showing high sensitivity and reproducible testing results

Intrinsic variability of nanoscale CMOS technology for logic and memory.

The continuous downscaling of CMOS technology, the main engine of development of the semiconductor Industry, is limited by factors that become important for nanoscale device size, which undermine proper device operation completely offset gains from scaling. One of the main problems is device variability: nominally identical devices are different at the microscopic level due to fabrication tolerance and the intrinsic granularity of matter. For this reason, structures, devices and materials for the next technology nodes will be chosen for their robustness to process variability, in agreement with the ITRS (International Technology Roadmap for Semiconductors). Examining the dispersion of various physical and geometrical parameters and the effect these have on device performance becomes necessary. In this thesis, I focus on the study of the dispersion of the threshold voltage due to intrinsic variability in nanoscale CMOS technology for logic and for memory. In order to describe this, it is convenient to have an analytical model that allows, with the assistance of a small number of simulations, to calculate the standard deviation of the threshold voltage due to the various contributions

Optimization and evaluation of variability in the programming window of a flash cell with molecular metal-oxide storage

We report a modeling study of a conceptual nonvolatile memory cell based on inorganic molecular metal-oxide clusters as a storage media embedded in the gate dielectric of a MOSFET. For the purpose of this paper, we developed a multiscale simulation framework that enables the evaluation of variability in the programming window of a flash cell with sub-20-nm gate length. Furthermore, we studied the threshold voltage variability due to random dopant fluctuations and fluctuations in the distribution of the molecular clusters in the cell. The simulation framework and the general conclusions of our work are transferrable to flash cells based on alternative molecules used for a storage media

Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks

This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are currents instead of voltages as presented in previous approaches, thus avoiding the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploitation of current mirror properties for the efficient implementation of both linear and nonlinear analog operators. These cells are simpler and easier to design than those found in previously reported CT and DT-CNN devices. Basic design issues are covered, together with discussions on the influence of nonidealities and advanced circuit design issues as well as design for manufacturability considerations associated with statistical analysis. Three prototypes have been designed for l.6-pm n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. Experimental results are given illustrating performance of these prototypes

Statistical compact model strategies for nano CMOS transistors subject of atomic scale variability

One of the major limiting factors of the CMOS device, circuit and system simulation in sub 100nm regimes is the statistical variability introduced by the discreteness of charge and granularity of matter. The statistical variability cannot be eliminated by tuning the layout or by tightening fabrication process control. Since the compact models are the key bridge between technology and design, it is necessary to transfer reliably the MOSFET statistical variability information into compact models to facilitate variability aware design practice. The aim of this project is the development of a statistical extraction methodology essential to capture statistical variability with optimum set of parameters particularly in industry standard compact model BSIM. This task is accomplished by using a detailed study on the sensitivity analysis of the transistor current in respect to key parameters in compact model in combination with error analysis of the fitted Id-Vg characteristics. The key point in the developed direct statistical compact model strategy is that the impacts of statistical variability can be captured in device characteristics by tuning a limited number of parameters and keeping the values for remaining major set equal to their default values obtained from the “uniform” MOSFET compact model extraction. However, the statistical compact model extraction strategies will accurately represent the distribution and correlation of the electrical MOSFET figures of merit. Statistical compact model parameters are generated using statistical parameter generation techniques such as uncorrelated parameter distributions, principal component analysis and nonlinear power method. The accuracy of these methods is evaluated in comparison with the results obtained from ‘atomistic’ simulations. The impact of the correlations in the compact model parameters has been analyzed along with the corresponding transistor figures of merit. The accuracy of the circuit simulations with different statistical compact model libraries has been studied. Moreover, the impact of the MOSFET width/length on the statistical trend of the optimum set of statistical compact model parameters and electrical figures of merit has been analyzed with two methods to capture geometry dependencies in proposed statistical models

Remediation of contaminated marine sediment using bentonite, kaolin and sand as capping materials

There is a growing public concern over the issue of sediment contamination resulting from industrial, municipal wastewater, mining activities, and improper use of chemical fertilizer or pesticides. The conventional treatment of contaminated sediment is dredging, but this treatment is expensive and requires a large area of land for disposal. In situ capping of contaminated sediment is considered as a cheaper technique compared to dredging and efficient treatment technology to immobilize pollutants in sediments on site. In this technique, sediments are capped by placing a layer of inert materials like sand, clean soil, or gravel or active materials like activated carbon, zeolite, or apatite over sediments in order to reduce the risk to the aquatic environment. The objective of this study is to determine the effectiveness of using active materials; bentonite (B), kaolin (K), mixture of bentonite with kaolin (1:1) (BK) as capping materials to block the release of five heavy metals (Pb, Cr, Cu, Cd and Zn) from artificially polluted sediments. The effectiveness of B, K, and BK for preventing the leachability of the trace metals was assessed on a bench-scale laboratory experiment in glass tanks for 90 days, where 1cm thick layer of capping material and sand was placed above the contaminated sediment. The results showed that B and BK reduced the leachability of Pb, Cr, and Cu from the sediments. The results also showed that B and BK could be used as potential capping materials for the remediation of contaminated sites due to their significant entrapping of Pb, Cu, and Cr. The pollutants were released into the overlying water from the contaminated sediment in the following decreasing order; Cd > Zn > Pb > Cu > Cr. The adsorption kinetics analysis also showed that the process of adsorption was by chemisorption. This study proved that bentonite and mixture of bentonite with kaolin clays covered with sand could be used as capping materials for in situ treatment of Pb, Cu, Cr, Zn, and Cd for contaminated marine sediment