Modeling of thermally induced skew variations in clock distribution network

Clock distribution network is sensitive to large thermal gradients on the die as the performance of both clock buffers and interconnects are affected by temperature. A robust clock network design relies on the accurate analysis of clock skew subject to temperature variations. In this work, we address the problem of thermally induced clock skew modeling in nanometer CMOS technologies. The complex thermal behavior of both buffers and interconnects are taken into account. In addition, our characterization of the temperature effect on buffers and interconnects provides valuable insight to designers about the potential impact of thermal variations on clock networks. The use of industrial standard data format in the interface allows our tool to be easily integrated into existing design flow

Commercial Off-The-Shelf (COTS) Parts Risk and Reliability User and Application Guide

All COTS parts are not created equal. Because they are not created equal, the notion that one can force the commercial industry to follow a set of military specifications and standards, along with the certifications, audits and qualification commitments that go with them, is unrealistic for the sale of a few parts. The part technologies that are Defense Logistics Agency (DLA) certified or Military Specification (MS) qualified, are several generations behind the state-of-the-art high-performance parts that are required for the compact, higher performing systems for the next generation of spacecraft and instruments. The majority of the part suppliers are focused on the portion of the market that is producing high-tech commercial products and systems. To that end, in order to compete in the high performance and leading edge advanced technological systems, an alternative approach to risk assessment and reliability prediction must be considered

Integrated Circuit for Subnanosecond Gating of InGaAs/InP SPAD

We present a novel integrated circuit for subnanosecond gating of InGaAs/InP single-photon avalanche diodes (SPADs). It enables the detector in well-defined time intervals (down to 500 ps) and strongly reduces the afterpulsing effect. It includes a fast pulser with rising/falling edge shorter than 300 ps (20%-80%), a wideband comparator and hold-off logic circuitry. The fast avalanche quenching reduces the charge flow in the SPAD, thus decreasing the afterpulsing, a detrimental effect that limits the maximum count rate of InGaAs/InP SPADs. The wideband SiGe comparator guarantees very low timing jitter of the acquired waveforms: <100 ps (FWHM) at 5 V excess bias voltage, when operated with InGaAs/InP SPAD, whereas we estimate that the time jitter of the circuit is < 30 ps

Voltage fluctuations in IC power supply distribution

The supply voltage decrease and power consumption increase of modern ICs made the requirements for low voltage fluctuation caused by packaging and on-chip parasitic impedances more difficult to achieve. Most of the research works on the area assume that all the nodes of the chip are fed at the same voltage, in such a way that the main cause of disturbance or fluctuation is the parasitic impedance of packaging. In the paper an approach to analyze the effect of high and fast current demands on the on-chip power supply network. First an approach to model the entire network by considering a homogeneous conductive foil is presented. The modification of the timing parameters of flipflops caused by spatial voltage drops through the IC surface are also investigated.Peer Reviewe

Transistor Degradations in Very Large-Scale-Integrated CMOS Technologies

The historical evolution of hot carrier degradation mechanisms and their physical models are reviewed and an energy-driven hot carrier aging model is verified that can reproduce 62-nm-gate-long hot carrier degradation of transistors through consistent aging-parameter extractions for circuit simulation. A long-term hot carrier-resistant circuit design can be realized via optimal driver strength controls. The central role of the V GS ratio is emphasized during practical case studies on CMOS inverter chains and a dynamic random access memory (DRAM) word-line circuit. Negative bias temperature instability (NBTI) mechanisms are also reviewed and implemented in a hydrogen reaction-diffusion (R-D) framework. The R-D simulation reproduces time-dependent NBTI degradations interpreted into interface trap generation, Δ N it with a proper power-law dependency on time. The experimental evidence of pre-existing hydrogen-induced Si–H bond breakage is also proven by the quantifying R-D simulation. From this analysis, a low-pressure end-of-line (EOL) anneal can reduce the saturation level of NBTI degradation, which is believed to be caused by the outward diffusion of hydrogen from the gate regions and therefore prevents further breakage of Si–H bonds in the silicon-oxide interfaces

Addressing Manufacturing Challenges in NoC-based ULSI Designs

Hernández Luz, C. (2012). Addressing Manufacturing Challenges in NoC-based ULSI Designs [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/1669

Techniques for low power analog, digital and mixed signal CMOS integrated circuit design

With the continuously expanding of market for portable devices such as wireless communication devices, portable computers, consumer electronics and implantable medical devices, low power is becoming increasingly important in integrated circuits. The low power design can increase operation time and/or utilize a smaller size and lighter-weight battery. In this dissertation, several low power complementary metal-oxide-semiconductor (CMOS) integrated circuit design techniques are investigated. A metal-oxide-semiconductor field effect transistor (MOSFET) can be operated at a lower voltage by forward-biasing the source-substrate junction. This approach has been investigated in detail and used to designing an ultra-low power CMOS operational amplifier for operation at ± 0.4 V. The issue of CMOS latchup and noise has been investigated in detail because of the forward biasing of the substrates of MOSFETs in CMOS. With increasing forward body-bias, the leakage current increases significantly. Dynamic threshold MOSFET (DTMOS) technique is proposed to overcome the drawback which is inherent in a forward-biased MOSFET. By using the DTMOS method with the forward source-body biased MOSFET, two low-power low-voltage CMOS VLSI circuits that of a CMOS analog multiplexer and a Schmitt trigger circuits are designed. In this dissertation, an adaptive body-bias technique is proposed. Adaptive body-bias voltage is generated for several operational frequencies. Another issue, which the chip design community is facing, is the development of portable, cost effective and low power supply voltage. This dissertation proposes a new cost-effective DC/DC converter design in standard 1.5 um n-well CMOS, which adopts a delay-line controller for voltage regulation

Energy challenges for ICT

The energy consumption from the expanding use of information and communications technology (ICT) is unsustainable with present drivers, and it will impact heavily on the future climate change. However, ICT devices have the potential to contribute signi - cantly to the reduction of CO2 emission and enhance resource e ciency in other sectors, e.g., transportation (through intelligent transportation and advanced driver assistance systems and self-driving vehicles), heating (through smart building control), and manu- facturing (through digital automation based on smart autonomous sensors). To address the energy sustainability of ICT and capture the full potential of ICT in resource e - ciency, a multidisciplinary ICT-energy community needs to be brought together cover- ing devices, microarchitectures, ultra large-scale integration (ULSI), high-performance computing (HPC), energy harvesting, energy storage, system design, embedded sys- tems, e cient electronics, static analysis, and computation. In this chapter, we introduce challenges and opportunities in this emerging eld and a common framework to strive towards energy-sustainable ICT

CMOS analog integrated circuit design techniques for low-powered ubiquitous device

制度:新 ; 文部省報告番号:甲2633号 ; 学位の種類:博士(工学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新479