Electrical degradation mechanisms of RF power GaAs PHEMTs

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Vita.Includes bibliographical references (p. 155-161).GaAs Pseudomorphic High-Electron Mobility Transistors (PHEMTs) are widely used in RF power applications. Since these devices typically operate at high power levels and under high voltage biasing, their electrical reliability is of serious concern. Previous studies have identified several distinct degradation phenomena in these devices, but a complete picture has yet to be formed. In this study, we have carried out a comprehensive study of the mechanisms of electrical degradation on a set of experimental RF power GaAs PHEMTs (non-commercial devices provided by our sponsor, Mitsubishi Electric). A wide variety of electrical stressing experiments employing different conditions (varying temperature, bias, environment) were performed on these devices in order to monitor their degradation with stressing. Our general observations showed several forms of degradation, the most concerning being an increase in the drain resistance RD and a reduction in maximum drain current Imax. Contrary to what is often claimed in the literature, our experiments indicated that these forms of degradation were not driven by impact-ionization or hot-electron effects. Instead, we found the degradation to be strongly correlated with temperature, stressing environment, and drain-gate bias, which were all consistent with a corrosion mechanism. Via materials analysis we were able to confirm that the degradation of both RD and Imax were due to surface corrosion on the drain side of the device, albeit at different specific locations. The increase in RD was attributed to oxidation on the n+GaAs ledge, while the reduction in Imax was due to oxidation on the AlGaAs surface, closer to the gate.(cont.) A recoverable negative shift in the threshold voltage VT and a permanent decrease in Rs were also observed during electrical stressing. The shift in VT was attributed to field-assisted tunneling of electrons out of traps under the gate, while the decrease in Rs was found to be consistent with recombination-induced annealing of defects on the source side of the device. Measurements were also performed to observe light emitted from the device during electrical stressing. The observed light-emission indicated that device degradation was proceeding in a highly non-uniform manner across the width of the device, due to a non-uniform electric field distribution. We attributed this to a non-uniform recess geometry across the device width. This suggested that it is important to ensure uniform geometry across the device width, in order to minimize non-uniformities in electric field distribution and enhance device reliability. The physical understanding developed in this work should be instrumental to identifying and addressing future reliability issues in RF power GaAs PHEMTs.by Anita Villanueva.Ph.D

Investigation And Trade Study On Hot Carrier Reliability Of The Phemt For Dc And Rf Performance

A unified study on the hot carrier reliability of the Pseudomorphic High Electron Mobility Transistor (PHEMT) is carried out through Sentaurus Device Simulation, measurement, and physical analyses. A trade study of devices with four various geometries are evaluated for DC and RF performance. The trade-off of DC I-V characteristics, transconductance, and RF parameters versus hot carrier induced gate current is assessed for each device. Ambient temperature variation is also evaluated to observe its impact on hot carrier effects. A commercial grade PHEMT is then evaluated and measured to demonstrate the performance degradation that occurs after a period of operation in an accelerated stress regime— one hour of high drain voltage, low drain current stress. This stress regime and normal operation regime are then modeled through Sentaurus. Output characteristics are shown along with stress mechanisms within the device. Lastly, a means of simulating a PHEMT post-stress is introduced. The approach taken accounts for the activation of dopants near the channel. Post-stress simulation results of DC and RF performance are then investigated

ELECTRON DEVICE NONLINEAR MODELLING FOR MICROWAVE CIRCUIT DESIGN

The electron device modelling is a research topic of great relevance, since the performances required to devices are continuously increasing in terms of frequency, power and linearity: new technologies are affirming themselves, bringing new challenges for the modelling community. In addition, the use of monolithic microwave integrated circuits (MMIC) is also increasing, making necessary the availability, in the circuit design phase, of models which are computationally efficient and at the same more and more accurate. The importance of modelling is even more evident by thinking at the wide area covered by microwave systems: terrestrial broadband, satellite communications, automotive applications, but also military industry, emergency prevention systems or medical instrumentations. This work contains a review of the empirical modelling approach, providing the description of some well-known equivalent-circuit and black-box models. In addition, an original modelling approach is described in details, together with the various possible applications: modelling of nonquasi-static phenomena as well as of low-frequency dispersive effects. A wide experimental validation is provided, for GaAs- and GaN-based devices. Other modelling issues are faced up, like the extraction of accurate models for Cold-FET or the more convenient choice of the data-interpolator in table-based models. Finally, the device degradation is also treated: a new measurement setup will be presented, aimed to the characterization of the device breakdown walkout under actual operating conditions for power amplifiers

Effect of varying gate-drain distance on the RF power performance of pseudomorphic high electron mobility transistors

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 134-137).AIGaAs/lnGaAs Pseudomorphic High Electron Mobility Transistors (PHEMTs) are widely used in satellite communications, military and commercial radar, cellular telephones, and other RF power applications. One key figure of merit in these applications is RF power output. Increasing the gate-to-drain length (LRD) of the PHEMT leads to an increase in its breakdown voltage. This should theoretically allow the selection of a higher drain operating voltage and consequently result in higher output power at microwave frequencies. However, experimentally, a decrease in output power and peak power-added efficiency is generally observed with increasing LRD In order to understand this, we have studied in detail the RF power performance of industrial PHEMTs with different values of LRD. We have found that there is an optimum value of LRD beyond which the maximum RF power output that the device can deliver drops. In addition, we have found that the output power of long LRD devices declines significantly with increasing frequency. We explain the difference in RF power behavior of the different devices through the evolution of load lines with frequency, LRD, and operating voltage. We have found that the presence of oscillations in the NDR region limit the maximum allowable operating voltage of long LRD devices through catastrophic burnout. The maximum voltage of short LRD devices is limited by electrical degradation. Pulsed I-V measurements have revealed that long LRD devices increasingly suffer from surface state activity that limit the maximum drain current under RF operation. A delay time analysis has shown an increasing extension of the depletion region toward the drain with increasing LRD that limits the frequency response of long LRD devices.by Melinda F. Wong.S.M

The development of sub-25 nm III-V High Electron Mobility Transistors

High Electron Mobility Transistors (HEMTs) are crucially important devices in microwave circuit applications. As the technology has matured, new applications have arisen, particularly at millimetre-wave and sub-millimetre wave frequencies. There now exists great demand for low-visibility, security and medical imaging in addition to telecommunications applications operating at frequencies well above 100 GHz. These new applications have driven demand for high frequency, low noise device operation; key areas in which HEMTs excel. As a consequence, there is growing incentive to explore the ultimate performance available from such devices. As with all FETs, the key to HEMT performance optimisation is the reduction of gate length, whilst optimally scaling the rest of the device and minimising parasitic extrinsic influences on device performance. Although HEMTs have been under development for many years, key performance metrics have latterly slowed in their evolution, largely due to the difficulty of fabricating devices at increasingly nanometric gate lengths and maintaining satisfactory scaling and device performance. At Glasgow, the world-leading 50 nm HEMT process developed in 2003 had not since been improved in the intervening five years. This work describes the fabrication of sub-25 nm HEMTs in a robust and repeatable manner by the use of advanced processing techniques: in particular, electron beam lithography and reactive ion etching. This thesis describes firstly the development of robust gate lithography for sub-25 nm patterning, and its incorporation into a complete device process flow. Secondly, processes and techniques for the optimisation of the complete device are described. This work has led to the successful fabrication of functional 22 nm HEMTs and the development of 10 nm scale gate pattern transfer: simultaneously some of the shortest gate length devices reported and amongst the smallest scale structures ever lithographically defined on III-V substrates. The first successful fabrication of implant-isolated planar high-indium HEMTs is also reported amongst other novel secondary processes