186 research outputs found
Gate-source distance scaling effects in H-terminated diamond MESFETs
In this paper, an analysis of gate-source and gate-drain scaling effects in MESFETs fabricated on hydrogen-terminated single-crystal diamond films is reported. The experimental results show that a decrease in gate-source spacing can improve the device performance by increasing the device output current density and its transconductance. On the contrary, the gate--drain distance produces less pronounced effects on device performance. Breakdown voltage, knee voltage, and threshold voltage variations due to changes in gate-source and drain-source distances have also been investigated. The obtained results can be used as a design guideline for the layout optimization of H-terminated diamond-based MESFETs
Testing Methodologies for Power Electronic Devices With focus on MOSFETs and IGBTs
Metal Oxide Semiconductor Field Eļ¬ect Transistor (MOSF ET s) and Insu-lated Gate Bipolar Transistor (IGBT s); both are the state-of-the-art semiconductor switching devices.In this study an in-depth study of Metal Oxide Semiconductor (MOS) physics, cell structure and electrical characterization of MOSFETs and IGBTs has been con-ducted. The aim is to achieve a further improvement on the reliability and rugged-ness of these power electronic devices using ļ¬ndings of the research. These power devices have an extensive industrial and domestic applications, they are the building blocks of nearly all types of power electronic circuits, control systems and advanced digital data storages, laptop and phone chargers, motor drives in electric vehicle, PV converters, Wind converters, industrial heaters. Power electronic monitoring systems including DC to DC converters, DC to AC inverters, AC to DC rectiļ¬ers and AC to AC converter.Silvaco simulation and MATLAB modeling enabled the research to gain a vivid understanding of device operation MOS physics and all relevant electrical charac-teristics. The practical experiment side of the research includes high power semi-conductor devices characterization; testing of fabricated discrete devices comprising:(200V, 40A Silicon MOSFET; 1.2KV, 19A Silicon Carbide MOSFET; 600V, 20A and 40A Silicon IGBT; 1.2KV, 25A Silicon IGBT). Consequently, the research work gained an insight to the semiconductor switching latest technologies that are useful for the optimization consideration of power electronic devices. Observations from published journals enabled to see the existing relevant research gaps and works car-ried out by other scientists around this ļ¬eld area. Silicon is the working material for this masterās by research thesis. Moreover, this paper also looks into the great beneļ¬ts of using silicon-carbide as a material for the next generation technological innovations.Therefore, this research contributes towards device optimization in the following way:Firstly, at a single cell design level. Shielded trench gate geometry architecture outperforms planar gate structure. Secondly, fabricating using a Wide-band-gap material (WBG) enhances device performance greatly
Wide Bandgap Based Devices
Emerging wide bandgap (WBG) semiconductors hold the potential to advance the global industry in the same way that, more than 50 years ago, the invention of the silicon (Si) chip enabled the modern computer era. SiC- and GaN-based devices are starting to become more commercially available. Smaller, faster, and more efficient than their counterpart Si-based components, these WBG devices also offer greater expected reliability in tougher operating conditions. Furthermore, in this frame, a new class of microelectronic-grade semiconducting materials that have an even larger bandgap than the previously established wide bandgap semiconductors, such as GaN and SiC, have been created, and are thus referred to as āultra-wide bandgapā materials. These materials, which include AlGaN, AlN, diamond, Ga2O3, and BN, offer theoretically superior properties, including a higher critical breakdown field, higher temperature operation, and potentially higher radiation tolerance. These attributes, in turn, make it possible to use revolutionary new devices for extreme environments, such as high-efficiency power transistors, because of the improved Baliga figure of merit, ultra-high voltage pulsed power switches, high-efficiency UV-LEDs, and electronics. This Special Issue aims to collect high quality research papers, short communications, and review articles that focus on wide bandgap device design, fabrication, and advanced characterization. The Special Issue will also publish selected papers from the 43rd Workshop on Compound Semiconductor Devices and Integrated Circuits, held in France (WOCSDICE 2019), which brings together scientists and engineers working in the area of IIIāV, and other compound semiconductor devices and integrated circuits
Comprehensive Mapping and Benchmarking of Esaki Diode Performance
The tunneling-FET (TFET) has been identified as a prospective MOSFET replacement technology with the potential to extend geometric and electrostatic scaling of digital integrated circuits. However, experimental demonstrations of the TFET have yet to reliably achieve drive currents necessary to power large scale integrated circuits. Consequentially, much effort has gone into optimizing the band-to-band tunneling (BTBT) efficiency of the TFET. In this work, the Esaki tunnel diode (ETD) is used as a short loop element to map and optimize BTBT performance for a large design space. The experimental results and tools developed for this work may be used to (1) map additional and more complicated ETD structures, (2) guide development of improved TFET structures and BTBT devices, (3) design ETDs targeted BTBT characteristics, and (4) calibrate BTBT models. The first objective was to verify the quality of monolithically integrated III-V based ETDs on Si substrates (the industry standard). Five separate GaAs/InGaAs ETDs were fabricated on GaAs-virtual substrates via aspect ratio trapping, along with two companion ETDs grown on Si and GaAs bulk substrates. The quality of the virtual substrates and BTBT were verified with (i) very large peak-valley current ratios (up to 56), (ii) temperature measurements, and (iii) deep sub-micron scaling. The second objective mapped the BTBT characteristics of the In1-xGaxAs ternary system by (1) standardizing the ETD structure, (2) limiting experimental work to unstrained (i) GaAs, (ii) In0.53Ga0.47As, and (iii) InAs homojunctions, and (3) systematically varying doping concentrations. Characteristic BTBT trendlines were determined for each material system, ranging from ultra-low to ultra-high peak current densities (JP) of 11 Ī¼A/cm2 to 975 kA/cm2 for GaAs and In0.53Ga0.47As, respectively. Furthermore, the BTBT mapping results establishes that BTBT current densities can only be improved by ~2-3 times the current record, by increasing doping concentration and In content up to ~75%. The E. O. Kane BTBT model has been shown to accurately predict the tunneling characteristics for the entire design space. Furthermore, it was used to help guide the development of a new universal BTBT model, which is a closed form exponential using 2 fitting parameters, material constants, and doping concentrations. With it, JP can quickly be predicted over the entire design space of this work
Simulation of FinFET Structures
The intensive downscaling of MOS transistors has been the major driving force behind the aggressive increases in transistor density and performance, leading to more chip functionality at higher speeds. While on the other side the reduction in MOSFET dimensions leads to the close proximity between source and drain, which in turn reduces the ability of the gate electrode to control the potential distribution and current flow in the channel region and also results in some undesirable effects called the short-channel effects. These limitations associated with downscaling of MOSFET device geometries have lead device designers and researchers to number of innovative techniques which include the use of different device structures, different channel materials, different gate-oxide materials, different processes such as shallow trench isolation, source/drain silicidation, lightly doped extensions etc. to enable controlled device scaling to smaller dimensions. A lot of research and development works have been done in these and related fields and more remains to be carried out in order to exploit these devices for the wider applications
Development of advanced technologies for the fabrication of III-V high electron mobility transistors
Over the past 5 years there has been an increase in the number of applications that require
devices that operate in the millimetre range (30-300GHz). This demand has driven research into
" devices that will operate at frequencies above 100GHz. This performance has been achieved
using two main technologies, the Heterojunction Bipolar Transistor (HBT) and the High
Electron Mobility Transistor (HEMT). At present it is a HEMT device that holds the record for
the highest operating frequency of any transistor. It is this technology that this project
concentrates on.
In order to fabricate devices that operate at these frequencies two methods are commonly
employed. The first is to vary the material of the device, in particular, increasing the indium
content of the channel. The second method is to reduce the physical dimensions of the
transistors, including reducing the gate length of the device therefore reducing transit time and
gate capacitance. Reducing the separation of the source-drain ohmic contacts or employing a
self-aligned ohmic strategy reduces the associated parasitic resistances. This project will
concentrate on the scaling of the gate length in addition to the reduction of parasitic resistances
with the use of self-aligned ohmic contacts.This work includes the realisation of the first self-aligned 120nm T -Gate. GaAs pHEMT
fabricated at the University of Glasgow. These devices required the development of two key
technologies, the non-annealed ohmic contact and the succinic acid based selective wet etch.
The self-aligned devices showed good RF performance with a ft of 150 GHz and a fmax of 180
GHz which compares favourable with results o~ 120nm GaAs pHEMTs previously fabricated at Glasgow.
The investigation of gate length scaling to device performance included the development of two
lithographic process capable of producing HEMT with a gate length of 50nm and 30nm respectively in addition to a method ~f sample preparation that allows these devices to be
analysed using TEM techniques.
This work has lead to the realisation of SOnm T -gate metamorphic HEMTs using a
PMMAIcopolymer resist stack, these devices displayed an excellent yield, with over 95% of
devices working. The uniformity of the gate process was also high with a threshold voltage of -
0.44SV with a standard deviation of O.OOSV. The devices demonstrated an .it of 330GHz and a
fmax of 260GHz making these devices some of the fastest transistors that have ever been
fabricated on a GaAs substrate. The second lithography process was developed to realise T -gates with a gate length of less than
SOnm. This processed used a two stage "bi-lithography" process to minimise the effect of
forward s7attering through the resist. The gate footprint was transferred into a Si02 gate by a dry
etch process. This lithography process was integrated into a full process flow for lattice matched
InP HEMTs Using this process, HEMTs were fabricated with a T-gate of 2Snm. This is the
smallest T -gate device that has been fabricated at the University of Glasgow and is comparable
with the smallest HEMT devices in the world
Investigation of the electrical properties of Siā-ĆGeĆ channel pMOSFETs with high-Īŗ dielectrics
It is now apparent that the continued performance enhancements of silicon metal-oxide-semiconductor field effect transistors (MOSFETs) can no longer be met by scaling alone. High-mobility channel materials such as strained Si1-xGex and Ge are now being seriously considered to maintain the performance requirements specified by the semiconductor industry. In addition, alternative gate dielectric, or high-Īŗ dielectrics, will also be required to meet gate leakage requirements.
This work investigates the properties of using strained Si1-xGex or Ge as alternative channel materials for pMOSFETs incorporating hafnium oxide (HfO2) high-Īŗ gate dielectric. Whilst the SiGe pMOSFETs (x = 0.25) exhibited an enhancement in hole mobility (300 K) over comparable silicon control pMOSFETs with sputtered HfO2 dielectric, high Coulomb scattering and surface roughness scattering relating to the dielectric deposition process meant that the effective hole mobilities were degraded with respect to the silicon universal curve.
Germanium channel pMOSFETs with halo-doping and HfO2 gate dielectric deposited by atomic layer deposition showed high hole mobilities of 230 cm2V-1s-1 and 480 cm2V-1s-1 at room temperature and 77 K, respectively. Analysis of the off-state current for the Ge pMOSFETs over a range of temperatures indicated that band-to-band tunnelling, gate-induced drain leakage and other defect-assisted leakage mechanisms could all be important.
Hole carrier velocity and impact ionisation were also studied in two batches of buried channel SiGe pMOSFET with x = 0.15 and x = 0.36, respectively. SiGe channel pMOSFETs were found to exhibit reduced impact ionisation compared to silicon control devices, which has been attributed to a strain-induced reduction of the density of states in the SiGe conduction and valence bands. Analysis of the hole carrier velocity indicated that pseudomorphic SiGe offered no performance enhancements over Si below 100 nm, possibly due to higher ion implantation damage and strain relaxation of the strained SiGe channel. The results indicate that velocity overshoot effects might not provide the performance improvements at short channel lengths that was previously hoped for
Characterizing and Modeling Transient Behavior in Power Electronic Circuits with Wide Bandgap Semiconductors and in Maximum Power Point Tracking for Photovoltaic Systems
This dissertation examines the transient characteristics in next generation power electronic circuits at both the device-level and the systems-level. At the device-level, the effect of the parasitic capacitances on the switching performance of emerging wide bandgap semiconductors (WBG) is evaluated. Equivalent device models based on gallium nitride (GaN) and silicon carbide (SiC) are implemented in SaberRD and MATLAB, and transient switching characteristics are analyzed in great detail. The effects of the parasitic capacitances on detrimental circuit behavior such as āovershoot,ā āringing,ā and āfalse turn-onā are investigated. The modeled results are supplemented and validated with experimental characterization of the devices in various power conversion circuits. The models can be used to aid in the design of next generation WBG devices so that the undesirable transient effects displayed by contemporary versions of these devices can be mitigated.
At the systems-level, the transient overshoot demonstrated by conventional maximum power point tracking algorithms for photovoltaic power conversion systems is investigated. An adaptive controller is implemented so that the operating point can converge to the optimal power point rapidly with minimal overshoot. This new controller overcomes the parasitic components inherent to the power converter which limit its ability to deliver maximum power rapidly. It will be shown that with the new controller, the maximum power point is attainable in 4 milliseconds.
The work accomplished in this dissertation lays a foundation for power electronic engineers to integrate semiconductor device theory with control theory to optimize the performance of next generation power conversion systems
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