Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test

Field test is performed in diverse environments, in which temperature varies across a wide range. As temperature affects a circuit delay greatly, accurate temperature monitors are required. They should be placed at various locations on a chip including hot spots. This paper proposes a flexible ring-oscillator-based monitor that accurately measures voltage as well as temperature at the same time. The measurement accuracy was confirmed by circuit simulation for 180 nm, 90 nm and 45 nm technologies. An experiment using test chips with 180 nm technology shows its feasibility.2014 IEEE 23rd Asian Test Symposium (ATS), 16-19 Nov. 2014, Hangzhou, Chin

Index to NASA Tech Briefs, 1975

This index contains abstracts and four indexes--subject, personal author, originating Center, and Tech Brief number--for 1975 Tech Briefs

A software controlled voltage tuning system using multi-purpose ring oscillators

This paper presents a novel software driven voltage tuning method that utilises multi-purpose Ring Oscillators (ROs) to provide process variation and environment sensitive energy reductions. The proposed technique enables voltage tuning based on the observed frequency of the ROs, taken as a representation of the device speed and used to estimate a safe minimum operating voltage at a given core frequency. A conservative linear relationship between RO frequency and silicon speed is used to approximate the critical path of the processor. Using a multi-purpose RO not specifically implemented for critical path characterisation is a unique approach to voltage tuning. The parameters governing the relationship between RO and silicon speed are obtained through the testing of a sample of processors from different wafer regions. These parameters can then be used on all devices of that model. The tuning method and software control framework is demonstrated on a sample of XMOS XS1-U8A-64 embedded microprocessors, yielding a dynamic power saving of up to 25% with no performance reduction and no negative impact on the real-time constraints of the embedded software running on the processor

Mixed Signal Integrated Circuit Design for Custom Sensor Interfacing

Low-power analog integrated circuits (ICs) can be utilized at the interface between an analog sensor and a digital system\u27s input to decrease power consumption, increase system accuracy, perform signal processing, and make the necessary adjustments for compatibility between the two devices. This interfacing has typically been done with custom integrated solutions, but advancements in floating-gate technologies have made reconfigurable analog ICs a competitive option. Whether the solution is a custom design or built from a reconfigurable system, digital peripheral circuits are needed to configure their operation for these analog circuits to work with the best accuracy.;Using an analog IC as a front end signal processor between an analog sensor and wireless sensor mote can greatly decrease battery consumption. Processing in the digital domain requires more power than when done on an analog system. An Analog Signal Processor (ASP) can allow the digital wireless mote to remain in sleep mode while the ASP is always listening for an important event. Once this event occurs, the ASP will wake the wireless mote, allowing it to record the event and send radio transmissions if necessary. As most wireless sensor networks employ the use of batteries as a power source, an energy harvesting system in addition to an ASP can be used to further supplement this battery consumption.;This thesis documents the development of mixed-signal integrated circuits for use as interfaces between analog sensors and digital Wireless Sensor Networks (WSNs). The following work outlines, as well as shows the results, of development for sensor interfacing utilizing both custom mixed signal integrated circuits as well as a Field Programmable Analog Array (FPAA) for post fabrication customization. An Analog Signal Processor (ASP) has been used in an Acoustic Vehicle Classification system. To keep these interfacing methods low power, a prototype energy harvesting system using commercial-off-the-shelf (COTS) devices is detailed which has led to the design of a fully integrated solution

Temperature Estimation Using Ring Oscillators

Partnering with C-4 Systems of General Dynamics in Needham, MA, this Worcester Polytechnic Institute Major Qualifying Project team explored the idea of designing a completely digital temperature sensor on field-programmable gate arrays. The goals of this MQP were (1) to find consistency between our research and results, and (2) to design a sensor capable of outputting a range of 0-70C, a resolution of 0.1C/count, and an error of +/-1C. Since propagation delay is dependent on temperature, we designed a ring oscillator out of logical inverters and counted the number of set clock periods to measure the length of the oscillator\u27s total delay. We implemented our design and determined its measuring capability to be 20-70C with an average resolution of ~0.13C/count and an error of +/-2.75C

Online Nbti Wear-out Estimation

CMOS feature size scaling has been a source of dramatic performance gains, but it has come at a cost of on-chip wear-out. Negative Bias Temperature Instability (NBTI) is one of the main on-chip wear-out problems which questions the reliability of a chip. To check the accuracy of Reaction-Diffusion (RD) model, this work first proposes to compare the NBTI wear-out data from the RD wear-out model and the reliability simulator - Ultrasim RelXpert, by monitoring the activity of the register file on a Leon3 processor. The simulator wear-out data obtained is considered to be the baseline data and is used to tune the RD model using a novel technique time slicing. It turns out that the tuned RD model NBTI degradation is on an average 80% accurate with respect to RelXpert simulator and its calculation is approximately 8 times faster than the simulator. We come up with a waveform compression technique, for the activity waveforms from the Leon3 register file, which consumes 131KB compared to 256MB required without compression, and also provides 91% accuracy in NBTI degradation, compared to the same obtained without compression. We also propose a NBTI ΔVth estimation/prediction technique to reduce the time consumption of the tuned RD model threshold voltage calculation by an order of with one day degradation being 93% within the same of the tuned RD model. This work further proposes to a novel NBTI Degradation Predictor (NDP), to predict the future NBTI degradation, in a DE2 FPGA for WCET benchmarks. Also we measure the ΔVth variation across the 4 corners of the DE2 FPGA running a single Leon3, which varies from 0.08% to 0.11% of the base Vth

Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA

Ring Oscillators are used for variety of purposes to enhance reliability on LSIs or FPGAs. This paper introduces an aging-tolerant design structure of ring oscillators that are used in FPGAs. The structure is able to reduce NBTI-induced degradation in a ring oscillator\u27s frequency by setting PMOS transistors of look-up tables in an off-state when the oscillator is not working. The evaluation of a variety of ring oscillators using Altera Cyclone IV device (60nm technology) shows that the proposed structure is capable of controlling degradation level as well as reducing more than 37% performance degradation compared to the conventional oscillators.The 20th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2014), Nov 19-21, 2014, Singapor

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input—driven by the analog input and by the reference slope generated by an FPGA output buffer—is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between −0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from −0.72 to 0.78 LSB