Analog Circuits in Ultra-Deep-Submicron CMOS

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena

An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction

In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a statistical model of average and rms currents of functional blocks and a high-level model of fanout distribution and interconnect wirelength. Following the 2001 SIA roadmap projections, we are able to predict a priori that the minimum width that satisfies the electromigration constraints does not scale like the minimum metal pitch in future technology nodes. As a consequence, the percentage of chip area covered by power lines is expected to increase at the expense of wiring resources unless proper countermeasures are taken. Some possible solutions are proposed in the paper

Impact of atomistic device variability on analogue circuit design

Scaling of complementary metal-oxide-semiconductor (CMOS) technology has benefited the semiconductor industry for almost half a century. For CMOS devices with a physical gate-length in the sub-100 nm range, extreme device variability is introduced and has become a major stumbling block for next generation analogue circuit design. Both opportunities and challenges have therefore confronted analogue circuit designers. Small geometry device can enable high-speed analogue circuit designs, such as data conversion interfaces that can work in the radio frequency range. These designs can be co-integrated with digital systems to achieve low cost, high-performance, single-chip solutions that could only be achieved using multi-chip solutions in the past. However, analogue circuit designs are extremely vulnerable to device mismatch, since a large number of symmetric transistor pairs and circuit cells are required. The increase in device variability from sub-100 nm processes has therefore significantly reduced the production yield of the conventional designs. Mismatch models have been developed to analytically evaluate the magnitude of random variations. Based on measurements from custom designed test structures, the statistics of process variation can be estimated using design related parameters. However, existing models can no longer accurately estimate the magnitude of mismatch for sub-100 nm “atomistic” devices, since short-channel effects have become important. In this thesis, a new mismatch model for small geometry devices will be proposed to address this problem. Based on knowledge of the matching performance obtained from the mismatch model, design solutions are desired at different design levels for a variety of circuit topologies. In this thesis, transistor level compensation solutions have been investigated and closed-loop compensation circuits have been proposed. At circuit level, a latch-based comparator has been used to develop a compensation solution because this type of comparator is extremely sensitive to the device mismatch. These comparators are also used as the fundamental building block for the analogue-to-digital converters (ADC). The proposed comparator compensation scheme is used to improve the performance of a high-speed flash ADC

Advanced compact modeling of the deep submicron technologies, Journal of Telecommunications and Information Technology, 2000, nr 3,4

The technology of CMOS large-scale integrated circuits (LSI’s) achieved remarkable advances over last 25 year and the progress is expected to continue well into the next century. The progress has been driven by the downsizing of the active devices such as MOSFETs. Approaching these dimensions, MOSFET characteristics cannot be accurately predicted using classical modeling methods currently used in the most common MOSFET models such as BSIM, MM9 etc, without introducing large number of empirical parameters. Various physical effects that needed to be considered while modeling UDSM devices: quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects, bias dependent source/drain resistances and capacitances, vertical and lateral doping profiles, etc. In this paper, we will discuss the progress in the CMOS technology and the anticipated difficulties of the sub-0.25 mm LSI downsizing. Subsequently, basic MOSFET modeling methodologies that are more appropriate for UDSM MOSFETs will be presented as well. The advances in compact MOSFET devices will be illustrated using application examples of the EPFL EKV model

A Charge-Recycling Scheme and Ultra Low Voltage Self-Startup Charge Pump for Highly Energy Efficient Mixed Signal Systems-On-A-Chip

The advent of battery operated sensor-based electronic systems has provided a pressing need to design energy-efficient, ultra-low power integrated circuits as a means to improve the battery lifetime. This dissertation describes a scheme to lower the power requirement of a digital circuit through the use of charge-recycling and dynamic supply-voltage scaling techniques. The novel charge-recycling scheme proposed in this research demonstrates the feasibility of operating digital circuits using the charge scavenged from the leakage and dynamic load currents inherent to digital design. The proposed scheme efficiently gathers the “ground-bound” charge into storage capacitor banks. This reclaimed charge is then subsequently recycled to power the source digital circuit. The charge-recycling methodology has been implemented on a 12-bit Gray-code counter operating at frequencies of less than 50 MHz. The circuit has been designed in a 90-nm process and measurement results reveal more than 41% reduction in the average energy consumption of the counter. The total energy savings including the power consumed for the generation of control signals aggregates to an average of 23%. The proposed methodology can be applied to an existing digital path without any design change to the circuit but with only small loss to the performance. Potential applications of this scheme are described, specifically in wide-temperature dynamic power reduction and as a source for energy harvesters. The second part of this dissertation deals with the design and development of a self-starting, ultra-low voltage, switched-capacitor (SC) DC-DC converter that is essential to an energy harvesting system. The proposed charge-pump based SC-converter operates from 125-mV input and thus enables battery-less operation in ultra-low voltage energy harvesters. The charge pump does not require any external components or expensive post-fabrication processing to enable low-voltage operation. This design has been implemented in a 130-nm CMOS process. While the proposed charge pump provides significant efficiency enhancement in energy harvesters, it can also be incorporated within charge recycling systems to facilitate adaptable charge-recycling levels. In total, this dissertation provides key components needed for highly energy-efficient mixed signal systems-on-a-chip

Journal of Telecommunications and Information Technology, 2000, nr 3,4

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Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

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Silicon on ferroelectric insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Title from PDF of title page, viewed on March 12, 2014Thesis advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 116-131)Thesis (M. S.)--School of Computer and Engineering. University of Missouri--Kansas City, 2013Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in subnanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor’s Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-lowpower applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.Abstract -- List of illustrations - List of tables -- Acknowledgements -- Dedication -- Introduction -- Carbon nanotube field effect transistor -- Multi-gate transistors -FinFET -- Subthreshold swing -- Tunneling field effect transistors -- I-mos and nanowire fets -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for soi-finfet -- Silicon-on-ferroelectric insulator field effect transistor (SOF-FET) -- Current-voltage characteristics of sof-fet -- Advantages, manufacturing process and future work of the proposed device -- Appendix -- Reference

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

Silicon on Ferroelectric Insulator Field Effect Transistor (SOFFET): A Radical Alternative to Overcome the Thermionic Limit

Title from PDF of title page viewed January 3,2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 165-180)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2016The path of down-scaling traditional MOSFET is reaching its technological, economic and, most importantly, fundamental physical limits. Before the dead-end of the roadmap, it is imperative to conduct a broad research to find alternative materials and new architectures to the current technology for the MOSFET devices. Beyond silicon electronic materials like group III-V heterostructure, ferroelectric material, carbon nanotubes (CNTs), and other nanowire-based designs are in development to become the core technology for non-classical CMOS structures. Field effect transistors (FETs) in general have made unprecedented progress in the last few decades by down-scaling device dimensions and power supply level leading to extremely high numbers of devices in a single chip. High density integrated circuits are now facing major challenges related to power management and heat dissipation due to excessive leakage, mainly due to subthreshold conduction. Over the years, planar MOSFET dimensional reduction was the only process followed by the semiconductor industry to improve device performance and to reduce the power supply. Further scaling increases short-channel-effect (SCE), and off-state current makes it difficult for the industry to follow the well-known Moore’s Law with bulk devices. Therefore, scaling planar MOSFET is no longer considered as a feasible solution to extend this law. The down-scaling of metal-oxide-semiconductor field effect transistors (MOSFETs) leads to severe short-channel-effects and power leakage at large-scale integrated circuits (LSIs). The device, which is governed by the thermionic emission of the carriers injected from the source to the channel region, has set a limitation of the subthreshold swing (S) of 60 / at room temperature. Devices with ‘S’ below this limit is highly desirable to reduce the power consumption and maintaining a high / current ratio. Therefore, the future of semiconductor industry hangs on new architectures, new materials or even new physics to govern the flow of carriers in new switches. As the subthreshold swing is increasing at every technology node, new structures using SOI, multi-gate, nanowire approach, and new channel materials such as III–V semiconductor have not satisfied the targeted values of subthreshold swing. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic emission limit of 60 /. This value was unbreakable by the new structure (SOI FinFET). On the other hand, most of the preview proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for sub-60 mV/decade designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This dissertation also proposes a novel design that exploits the concept of negative capacitance. The new field-effect-transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field effect-transistor (SOFFET). This proposal is a promising methodology for future ultra low-power applications because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers a subthreshold swing significantly lower than 60 / and reduced threshold voltage to form a conducting channel. The proposed SOFFET design, which utilizes the negative capacitance of a ferroelectric insulator in the body-stack, is completely different from the FeFET and NCFET designs. In addition to having the NC effect, the proposed device will have all the advantages of an SOI device. Body-stack that we are intending in this research has many advantages over the gate-stack. First, it is more compatible with the existing processes. Second, the gate and the working area of the proposed SOFFET is like the planar MOSFET. Third, the complexity and ferroelectric material interferences are shifted to the body of the device from the gate and the working area. The proposed structure offers better scalability and superior constructability because of the high-dielectric buried insulator. Here we are providing a very simplified model for the structure. Silicon-on-ferroelectric leads to several advantages including low off-state current and shift in the threshold voltage with the decrease of the ferroelectric material thickness. Moreover, having an insulator in the body of the device increases the controllability over the channel, which leads to the reduction in the short-channel-effect (SCE). The proposed SOFFET offers low value of subthreshold swing (S) leading to better performance in the on-state. The off-state current is directly related to S. So, the off-state current is also minimum in the proposed structure.Introduction -- Subthreshold swing -- Multi-gate devices -- Tunneling field effect transistors -- I-mos & FET transistors -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for SOI-FINFET -- Multichannel tunneling carbon nanotube FET -- Partially depleted silicon-on-Ferroelectric insulator FET -- Fully depleted silicon-on-ferroelectric insulator FET -- Advantages, manufacturing process, and future work of the proposed devices -- Appendix A. Estimation of the body factor (n) [eta] of SOI FinFET -- Appendix B. Solution for the Poisson Equation of MT-CNTFE