Robust Binary Neural Network Operation from 233 K to 398 K via Gate Stack and Bias Optimization of Ferroelectric FinFET Synapses

A synergistic approach for optimizing devices, circuits, and neural network architectures was used to abate junction-temperature-change-induced performance degradation of a Fe-FinFET-based artificial neural network. We demonstrated that the digital nature of the binarized neural network, with the "0" state programmed deep in the subthreshold and the "1" state in strong inversion, is crucial for robust DNN inference. The performance of a purely software-based binary neural network (BNN), with 96.1% accuracy for Modified National Institute of Standards and Technology (MNIST) handwritten digit recognition, was used as a baseline. The Fe-FinFET-based BNN (including device-to-device variation at 300 K) achieved 95.7% inference accuracy on the MNIST dataset. Although substantial inference accuracy degradation with temperature change was observed in a nonbinary neural network, the BNN with optimized Fe-FinFETs as synaptic devices had excellent resistance to temperature change effects and maintained a minimum inference accuracy of 95.2% within a temperature range of -233K to 398K after gate stack and bias optimization. However, reprogramming to adjust device conductance was necessary for temperatures higher than 398K.Comment: Accepted to be published in IEEE ED

FeFET-based Binarized Neural Networks Under Temperature-dependent Bit Errors

Ferroelectric FET (FeFET) is a highly promising emerging non-volatile memory (NVM) technology, especially for binarized neural network (BNN) inference on the low-power edge. The reliability of such devices, however, inherently depends on temperature. Hence, changes in temperature during run time manifest themselves as changes in bit error rates. In this work, we reveal the temperature-dependent bit error model of FeFET memories, evaluate its effect on BNN accuracy, and propose countermeasures. We begin on the transistor level and accurately model the impact of temperature on bit error rates of FeFET. This analysis reveals temperature-dependent asymmetric bit error rates. Afterwards, on the application level, we evaluate the impact of the temperature-dependent bit errors on the accuracy of BNNs. Under such bit errors, the BNN accuracy drops to unacceptable levels when no countermeasures are employed. We propose two countermeasures: (1) Training BNNs for bit error tolerance by injecting bit flips into the BNN data, and (2) applying a bit error rate assignment algorithm (BERA) which operates in a layer-wise manner and does not inject bit flips during training. In experiments, the BNNs, to which the countermeasures are applied to, effectively tolerate temperature-dependent bit errors for the entire range of operating temperature

Device modelling for bendable piezoelectric FET-based touch sensing system

Flexible electronics is rapidly evolving towards devices and circuits to enable numerous new applications. The high-performance, in terms of response speed, uniformity and reliability, remains a sticking point. The potential solutions for high-performance related challenges bring us back to the timetested silicon based electronics. However, the changes in the response of silicon based devices due to bending related stresses is a concern, especially because there are no suitable models to predict this behavior. This also makes the circuit design a difficult task. This paper reports advances in this direction, through our research on bendable Piezoelectric Oxide Semiconductor Field Effect Transistor (POSFET) based touch sensors. The analytical model of POSFET, complimented with Verilog-A model, is presented to describe the device behavior under normal force in planar and stressed conditions. Further, dynamic readout circuit compensation of POSFET devices have been analyzed and compared with similar arrangement to reduce the piezoresistive effect under tensile and compressive stresses. This approach introduces a first step towards the systematic modeling of stress induced changes in device response. This systematic study will help realize high-performance bendable microsystems with integrated sensors and readout circuitry on ultra-thin chips (UTCs) needed in various applications, in particular, the electronic skin (e-skin)

Fundamental design principles of novel MEMS based Landau switches, sensors, and actuators : Role of electrode geometry and operation regime

Microelectromechanical systems (MEMS) are considered as potential candidates for More-Moore and More-than-Moore applications due to their versatile use as sensors, switches, and actuators. Examples include accelerometers for sensing, RF-MEMS capacitive switches in communication, suspended-gate (SG) FETs in computation, and deformable mirrors in optics. In spite of the wide range of applications of MEMS in diverse fields, one of the major challenges for MEMS is their instability. Instability divides the operation into stable and unstable regimes and poses fundamental challenges for several applications. For example: Tuning range of deformable mirrors is fundamentally limited by pull-in instability, RF-MEMS capacitive switches suffer from the problem of hard landing, and intrinsic hysteresis of SG-FETs puts a lower bound on the minimum power dissipation. ^ In this thesis, we provide solutions to the application specific problems of MEMS and utilize operation in or close to unstable regime for performance enhancement in several novel applications. Specifically, we propose the following: (i) novel device concepts with nanostructured electrodes to address the aforementioned problems of instability, (ii) a switch with hysteresis-free ideal switching characteristics based on the operation in unstable regime, and (iii) a Flexure biosensor that operates at the boundary of the stable and unstable regimes to achieve improved sensitivity and signal-to-noise ratio. In general, we have advocated electrode geometry as a design variable for MEMS, and used MEMS as an illustrative example of Landau systems to advocate operation regime as a new design variabl

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Physics-Based Compact Model for p-GaN/AlGaN/GaN. Application: Understanding of Degradation After Gamma-Ray Irradiation

This thesis explores the nature of gallium nitride devices from the point of view of compact modeling paying particular attention to power electronic application. To model the behavior of such devices, the physics of the typical GaN HEMT is studied by solving the Schrodinger's and Poisson's equations. The Physical-Based model is used to help our understanding of the effect of gamma irradiation on GaN based devices

Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications

Growth and Oxidation of Graphene and Two-Dimensional Materials for Flexible Electronic Applications

The non-volatile storage of information is becoming increasingly important in our data-driven society. Limitations in conventional devices are driving the research and development of incorporating new materials into conventional device architectures to improve performance, as well as developing an array of emerging memory technologies based on entirely new physical processes. The discovery of graphene allowed for developing new approaches to these problems, both itself and as part of the larger, and ever-expanding family of 2D materials. In this thesis the growth and oxidation of these materials is investigated for implementing into such devices, exploiting some of the unique properties of 2D materials including atomic thinness, mechanical flexibility and tune-ability through chemical modification - to meet some challenges facing the community. This begins with the growth of graphene by chemical vapour deposition for a high quality flexible electrode material, followed by oxidation of graphene for use in resistive memory devices. The theme of oxidation is then extended to another 2D material, HfS2, which is selectively oxidised for use as high-k dielectric in Van der Waals heterostructures for FETs and resistive memory devices. Lastly, a technique for fabrication of graphene-based devices directly on the copper growth substrate is demonstrated for use in flexible devices for sensing touch and humidity

Ferroelectric Field Effect Transistor for Memory and Switch Applications

Silicon technology has advanced at exponential rates both in performances and productivity through the past four decades. However the limit of CMOS technology seems to be closer and closer and in the future we might see an increasing number of hybrid approaches where other technologies add to the CMOS performance, while maintaining a back-bone of CMOS logic. Ferro-electricity in ultra-thin films has been investigated as a credible candidate for nonvolatile memory thanks to the bistability of polarization. 1 transistor (1T) ferroelectric memory cells have been proposed and experimentally studied in order to reduce the size of 1T-1C (1Transistor-1Capacitor) design with consequent advantages in terms of size, read-out operation and costs. More recently ferroelectrics have been proposed by Salahuddin and Datta as dielectric materials in order to lower the 60mV/dec limit of the subthreshold swing (SS) in silicon Metal Oxide Semiconductor Field Effect Transistors, MOSFETs. The objective of this thesis is to study the ferroelectric transistor performance for both memory and switch application. For this purpose different Ferroelectric Field Effect Transistors, Fe-FETs, structures have been designed, fabricated and characterized. An organic ferroelectric polymer, vinylidene fluoride trifluorethylene, P(VDF-TrFE), of 100nm and 40nm thickness has been successfully integrated into the gate stack of bulk and SOI MOSFET and, later, on a Tunnel FET, TFET, structure. The 1T ferroelectric FET memory cells have shown a programming time in the order of ms at 9V as programming voltage. The retention of a few seconds, however, is the main limiting factor for the usage of this device for NV-memory applications. The retention failure mechanisms have been studied and investigated for future improvement. For the first time this work experimentally demonstrates that a subthreshold swing lower than 60mv/dec can be achieved in a ferroelectric transistor thanks to the voltage amplification arising from the ferroelectric material. This unique finding has been first measured in a 40nm P(VDF-TrFE)/10nm SiO2 gate stack MOSFET and then, confirmed, in a 100nm P(VDF-TrFE)/10nm SiO2 gate MOSFET with an intermediate contact between the two dielectrics. This internal node contact allows the study of the voltage amplification due to the ferroelectric material. Finally a temperature study of the performance of a ferroelectric Fully Depleted Silicon on Insulator, FD SOI, transistor has been done. A model based on Landau's theory has been carried out and it has been experimentally validated for both the subthreshold and the strong inversion regions. It has been demonstrated for the first time that, because of the divergence of the ferroelectric permittivity at the Curie temperature, Tc, a ferroelectric transistor has a maximum and a minimum, respectively of its transconductance and subthreshold swing, at Tc