43,723 research outputs found
Scalable Emulation of Sign-ProblemFree Hamiltonians with Room Temperature p-bits
The growing field of quantum computing is based on the concept of a q-bit
which is a delicate superposition of 0 and 1, requiring cryogenic temperatures
for its physical realization along with challenging coherent coupling
techniques for entangling them. By contrast, a probabilistic bit or a p-bit is
a robust classical entity that fluctuates between 0 and 1, and can be
implemented at room temperature using present-day technology. Here, we show
that a probabilistic coprocessor built out of room temperature p-bits can be
used to accelerate simulations of a special class of quantum many-body systems
that are sign-problemfree or stoquastic, leveraging the well-known
Suzuki-Trotter decomposition that maps a -dimensional quantum many body
Hamiltonian to a +1-dimensional classical Hamiltonian. This mapping allows
an efficient emulation of a quantum system by classical computers and is
commonly used in software to perform Quantum Monte Carlo (QMC) algorithms. By
contrast, we show that a compact, embedded MTJ-based coprocessor can serve as a
highly efficient hardware-accelerator for such QMC algorithms providing several
orders of magnitude improvement in speed compared to optimized CPU
implementations. Using realistic device-level SPICE simulations we demonstrate
that the correct quantum correlations can be obtained using a classical
p-circuit built with existing technology and operating at room temperature. The
proposed coprocessor can serve as a tool to study stoquastic quantum many-body
systems, overcoming challenges associated with physical quantum annealers.Comment: Fixed minor typos and expanded Appendi
Readiness of Quantum Optimization Machines for Industrial Applications
There have been multiple attempts to demonstrate that quantum annealing and,
in particular, quantum annealing on quantum annealing machines, has the
potential to outperform current classical optimization algorithms implemented
on CMOS technologies. The benchmarking of these devices has been controversial.
Initially, random spin-glass problems were used, however, these were quickly
shown to be not well suited to detect any quantum speedup. Subsequently,
benchmarking shifted to carefully crafted synthetic problems designed to
highlight the quantum nature of the hardware while (often) ensuring that
classical optimization techniques do not perform well on them. Even worse, to
date a true sign of improved scaling with the number of problem variables
remains elusive when compared to classical optimization techniques. Here, we
analyze the readiness of quantum annealing machines for real-world application
problems. These are typically not random and have an underlying structure that
is hard to capture in synthetic benchmarks, thus posing unexpected challenges
for optimization techniques, both classical and quantum alike. We present a
comprehensive computational scaling analysis of fault diagnosis in digital
circuits, considering architectures beyond D-wave quantum annealers. We find
that the instances generated from real data in multiplier circuits are harder
than other representative random spin-glass benchmarks with a comparable number
of variables. Although our results show that transverse-field quantum annealing
is outperformed by state-of-the-art classical optimization algorithms, these
benchmark instances are hard and small in the size of the input, therefore
representing the first industrial application ideally suited for testing
near-term quantum annealers and other quantum algorithmic strategies for
optimization problems.Comment: 22 pages, 12 figures. Content updated according to Phys. Rev. Applied
versio
Making Classical Ground State Spin Computing Fault-Tolerant
We examine a model of classical deterministic computing in which the ground
state of the classical system is a spatial history of the computation. This
model is relevant to quantum dot cellular automata as well as to recent
universal adiabatic quantum computing constructions. In its most primitive
form, systems constructed in this model cannot compute in an error free manner
when working at non-zero temperature. However, by exploiting a mapping between
the partition function for this model and probabilistic classical circuits we
are able to show that it is possible to make this model effectively error free.
We achieve this by using techniques in fault-tolerant classical computing and
the result is that the system can compute effectively error free if the
temperature is below a critical temperature. We further link this model to
computational complexity and show that a certain problem concerning finite
temperature classical spin systems is complete for the complexity class
Merlin-Arthur. This provides an interesting connection between the physical
behavior of certain many-body spin systems and computational complexity.Comment: 24 pages, 1 figur
Spin-Based Neuron Model with Domain Wall Magnets as Synapse
We present artificial neural network design using spin devices that achieves
ultra low voltage operation, low power consumption, high speed, and high
integration density. We employ spin torque switched nano-magnets for modelling
neuron and domain wall magnets for compact, programmable synapses. The spin
based neuron-synapse units operate locally at ultra low supply voltage of 30mV
resulting in low computation power. CMOS based inter-neuron communication is
employed to realize network-level functionality. We corroborate circuit
operation with physics based models developed for the spin devices. Simulation
results for character recognition as a benchmark application shows 95% lower
power consumption as compared to 45nm CMOS design
- …