OPTIMAL AREA AND PERFORMANCE MAPPING OF K-LUT BASED FPGAS

FPGA circuits are increasingly used in many fields: for rapid prototyping of new products (including fast ASIC implementation), for logic emulation, for producing a small number of a device, or if a device should be reconfigurable in use (reconfigurable computing). Determining if an arbitrary, given wide, function can be implemented by a programmable logic block, unfortunately, it is generally, a very difficult problem. This problem is called the Boolean matching problem. This paper introduces a new implemented algorithm able to map, both for area and performance, combinational networks using k-LUT based FPGAs.k-LUT based FPGAs, combinational circuits, performance-driven mapping.

Performance Comparison of Static CMOS and Domino Logic Style in VLSI Design: A Review

Of late, there is a steep rise in the usage of handheld gadgets and high speed applications. VLSI designers often choose static CMOS logic style for low power applications. This logic style provides low power dissipation and is free from signal noise integrity issues. However, designs based on this logic style often are slow and cannot be used in high performance circuits. On the other hand designs based on Domino logic style yield high performance and occupy less area. Yet, they have more power dissipation compared to their static CMOS counterparts. As a practice, designers during circuit synthesis, mix more than one logic style judiciously to obtain the advantages of each logic style. Carefully designing a mixed static Domino CMOS circuit can tap the advantages of both static and Domino logic styles overcoming their own short comings

Status of SuperSpec: A Broadband, On-Chip Millimeter-Wave Spectrometer

SuperSpec is a novel on-chip spectrometer we are developing for multi-object, moderate resolution (R = 100 - 500), large bandwidth (~1.65:1) submillimeter and millimeter survey spectroscopy of high-redshift galaxies. The spectrometer employs a filter bank architecture, and consists of a series of half-wave resonators formed by lithographically-patterned superconducting transmission lines. The signal power admitted by each resonator is detected by a lumped element titanium nitride (TiN) kinetic inductance detector (KID) operating at 100-200 MHz. We have tested a new prototype device that is more sensitive than previous devices, and easier to fabricate. We present a characterization of a representative R=282 channel at f = 236 GHz, including measurements of the spectrometer detection efficiency, the detector responsivity over a large range of optical loading, and the full system optical efficiency. We outline future improvements to the current system that we expect will enable construction of a photon-noise-limited R=100 filter bank, appropriate for a line intensity mapping experiment targeting the [CII] 158 micron transition during the Epoch of ReionizationComment: 16 pages, 10 figures, Proceedings of the SPIE Astronomical Telescopes + Instrumentation 2014 Conference, Vol 9153, Millimeter, Submillimeter, and Far-Infrared Detectors and Instrumentation for Astronomy VI

Switching Activity Minimization for XOR Gate Decomposition

In this paper we focus on reduction of switching activity in combinational logic circuits. We are analyzing energy consumption of multi-input XOR gate where changes of inputs occur principally at different times at logic level. We obtain upper and lower bounds for switching activity in various combinations with decomposition of muli-phase input gate. This work presents the algorithm of synthesis for multi-input XOR gate with minimum switching activity. The results presented in this paper are useful for power estimation and low power design. More than 10 to 70 % reduction of in switching activity has been observed using this method.Статья рассматривает вопросы минимизации переключательной активности комбинационных схем. Представлен анализ энергопотребления многовходовых элементов «Исключающее ИЛИ» для случая, когда сигналы на входах меняют свое состояние прин­ципиально в различные моменты времени. Получены формулы, определяющие верх­нюю и нижнюю границы переключательной активности для различных вариантов де­композиции многовходовых элементов. В работе представлен алгоритм синтеза многовходового элемента «Исключающее ИЛИ» с минимальной переключательной активностью. Полученные результаты могут быть использованы для оценки энергопотребления и проектирования с пониженным энергопотреблением. Показано, что применение предложенного подхода позволяет на 10–70 % снизить переключательную активность

Synthesis and Optimization of Reversible Circuits - A Survey

Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms --- search-based, cycle-based, transformation-based, and BDD-based --- as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table

Energy-aware embedded media processing: customizable memory subsystems and energy management policies

textThe design of energy-efficient data memory architectures for embedded system platforms has received considerable attention in recent years. In this dissertation we propose a special-purpose data memory subsystem, called Xtream-Fit, targeted to streaming media applications executing on both generic uniprocessor embedded platforms and powerful SMT-based multi-threading platforms. We empirically demonstrate that Xtream-Fit achieves high energydelay efficiency across a wide range of media devices, from systems running a single media application to systems concurrently executing multiple media applications under synchronization constraints. Xtream-Fit’s energy efficiency is predicated on a novel task-based execution model that exposes/enhances opportunities for efficient prefetching, and aggressive dynamic energy conservation techniques targeting on-chip and off-chip memory components. A key novelty of Xtream-Fit is that it exposes a single customization parameter, thus enabling a very simple and yet effective design space exploration methodology to find the best memory configuration for the target application(s). Extensive experimental results show that Xtream-Fit reduces energy-delay product substantially – by 32% to 69% – as compared to ‘standard’ general-purpose memory subsystems enhanced with state of the art cache decay and SDRAM power mode control policies.Electrical and Computer Engineerin

Integration of design tools and knowledge capture into a CAD system: a case study

onceptual design phase is partially supported by product lifecycle management/computer-aided design (PLM/CAD) systems causing discontinuity of the design information flow: customer needs — functional requirements — key characteristics — design parameters (DPs) — geometric DPs. Aiming to address this issue, it is proposed a knowledge-based approach is proposed to integrate quality function deployment, failure mode and effects analysis, and axiomatic design into a commercial PLM/CAD system. A case study, main subject of this article, was carried out to validate the proposed process, to evaluate, by a pilot development, how the commercial PLM/CAD modules and application programming interface could support the information flow, and based on the pilot scheme results to propose a full development framework