Innovative teaching of IC design and manufacture using the Superchip platform

In this paper we describe how an intelligent chip architecture has allowed a large cohort of undergraduate students to be given effective practical insight into IC design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the “Superchip”, has been developed, which allows multiple student designs to be fabricated on a single IC, and encapsulated in a standard package without excessive cost in terms of time or resources. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. Furthermore, the students are introduced at an early stage to the key concepts of team working, exposure to real deadlines and collaborative report writing. This paper provides details of the teaching rationale, design exercise overview, design process, chip architecture and test regime

On Timing Model Extraction and Hierarchical Statistical Timing Analysis

In this paper, we investigate the challenges to apply Statistical Static Timing Analysis (SSTA) in hierarchical design flow, where modules supplied by IP vendors are used to hide design details for IP protection and to reduce the complexity of design and verification. For the three basic circuit types, combinational, flip-flop-based and latch-controlled, we propose methods to extract timing models which contain interfacing as well as compressed internal constraints. Using these compact timing models the runtime of full-chip timing analysis can be reduced, while circuit details from IP vendors are not exposed. We also propose a method to reconstruct the correlation between modules during full-chip timing analysis. This correlation can not be incorporated into timing models because it depends on the layout of the corresponding modules in the chip. In addition, we investigate how to apply the extracted timing models with the reconstructed correlation to evaluate the performance of the complete design. Experiments demonstrate that using the extracted timing models and reconstructed correlation full-chip timing analysis can be several times faster than applying the flattened circuit directly, while the accuracy of statistical timing analysis is still well maintained

Implementation of a 4-bit Ripple Carry Full Adder of Mirror Design Style Using Synopsys Generic 90nm Technology on a Full-Custom and Semi-Custom Design

The most frequently used component in the datapath block and the speed-limiting element is the adder. Because of this, it is essential to optimize the adder knowing it has a big impact on the overall system performance. In addition to that, adders are a very important subsystem in digital designs, thus, taking care about its performance must be spotted. By manipulating the transistor sizes and circuit topology, the speed can be optimized. A circuit of a CMOS (Complementary metal oxide semiconductor) 4-bit RCA (Ripple Carry Adder) is presented. The proposed adder cell refers to the CMOS adder class executed on CMOS mirror design style that has a smaller area and delay compared with the static adder implementation of the full adder. By simply cascading full-adder blocks, one obtains a Ripple-Carry Adder which perhaps the simplest to implement than that of the other carry adders. Creating the full adder in schematic diagram is a part of Pre-simulation. It incorporates the construction of CMOS transistors and connected through the use of wires. Widths and lengths of the transistors are the crucial parts in designing to place and route connections easily. Layout diagram is the equivalent of the schematic diagram but more on a detailed part and it should be the same as the transistor based circuit. With the aid of the verification processes such as DRC (Design Rule Check) and LVS (Layout versus Schematic), it can give an assurance that both the schematic and layout diagrams are similar and functioning properly

Teaching integrated circuit and semiconductor device design in New Zealand: the University of Canterbury approach

Teaching the practical aspects of device and chip design in New Zealand presents many problems, including high manufacturing costs, long lead times, and the lack of local industry strength. Nonetheless, it is possible to overcome these issues. This paper describes the courses in these areas at the University of Canterbury, including a practical IC design project that has been running successfully for the past four years. The IC design project takes final year students through a full custom design using modern design tools and fabrication processes. The design is quite straightforward — a 4-bit arithmetic logic unit — but it emphasises the importance of design, simulation and testing. The final circuits contain a few hundred transistors, so good practice is essential. Twelve designs are integrated on to a single chip to keep costs down, and individual designs are addressed via multiplexers. The designs are fabricated using a 0.5 micron process, accessed through a multi-project vendor (MOSIS). Getting chips back from a manufacturer is significantly more motivating for the students than just performing a paper design

Logic circuit design verification support tool - Fit Board

AbstractLogic circuits knowledge is the cornerstone of all the courses devoted to digital systems design. Therefore, it is important to ensure a high level of knowledge, understanding as well as the skills of all the students of informatics and computer science study programs. The present study introduces a method to improve the students‟ results by the means of a multi-purpose virtual verification panel called FitBoard. The above mentioned tool is focused specifically on understanding and practicing the complete set of logic gates. However, the tool also provides many additional features. FitBoard is platform independent, easy to use, configurable for various tasks and restrictions and useful in learning as well as in the assessment process. Compared to the other available logic gates simulators, the simplicity and intuitive user interface of FitBoard enables the students to concentrate on the assigned tasks without first studying the usage. The data collected during the course proved a positive response from both the teachers as well as the students

Engineering at San Jose State University, Fall 2017

https://scholarworks.sjsu.edu/engr_news/1016/thumbnail.jp

An Alternative Way of Teaching Operational Amplifiers Using a Reconfigurable and Expandable Kit

Early on, students must develop competences by implementing simple or complex electronic circuits with Operational Amplifiers (OpAmps). Traditionally, these skills were mainly developed in laboratory classes, but technology allows us to explore other and complementary ways of aiding students in this achievement. This paper presents a contribution to improve the way OpAmps are included in electronic engineering courses’ curricula. A reconfigurable and expandable kit to teach electronic circuits based on the OpAmp uA741 was designed and implemented. This kit comprises a software application locally interfaced with a hardware platform capable of running in a PC. This platform includes a circuit with the OpAmp uA741 able to reconfigure according to a set of parameters defined by a software application. Its reconfiguration capability also enables the establishment of automatic connections for measuring and for applying signals to a reconfigured circuit, plus the ability to simulate the same or other OpAmp-based circuits. This paper provides an overview about the OpAmp uA741 and its relevance in engineering education. After presenting the kit and make some considerations for its improvement, at the end a brief discussion about its implementation in education according to specific educational strategies and methodologies are provided.This work was supported in part by the Fundação para a Ciência e Tecnologia under Grant FCT-UID-EQU-04730-2013info:eu-repo/semantics/publishedVersio