Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.Siirretty Doriast

Thermal performance enhancement of packaging substrates with integrated vapor chamber

The first part of this research investigates the effects of copper structures, such as copper through-package-vias (TPVs), and copper traces in redistribution layer (RDL), on the thermal performance of glass interposers through numerical and experimental approaches. Numerical parametric study on 2.5D interposers shows that as more copper structures are incorporated in glass interposers, the performance of silicon and glass interposers becomes closer, showing 31% difference in thermal resistance, compared to 53% difference without any copper structures in both interposers. In the second part of this study, a thermal model of glass interposer mounted on the vapor chamber integrated PCB is developed using multi-scale modeling scheme. The comparison of thermal performance between silicon and glass interposers shows that integration of vapor chamber with PCB makes thermal performance of both interposers almost identical, overcoming the limitation posed by low thermal conductivity of glass. The third part of this thesis focuses on design, fabrication, and performance measurement of PCB integrated with vapor chamber. Copper micropillar wick structure is fabricated on PCB with electroplating process, and its wettability is enhanced by silica nanoparticle coating. Design of the wick for the vapor chamber is determined based on the capillary performance and permeability test results. Fabricated device with ultra-thin thickness (~800 µm) shows higher thermal performance than copper plated PCB with the same thickness. Finally, 3D computational fluid dynamics/heat transfer model of the vapor chamber is developed, and modeling result is compared with test result.Ph.D

Electronics Thermal Management in Information and Communications Technologies: Challenges and Future Directions

This paper reviews thermal management challenges encountered in a wide range of electronics cooling applications from large-scale (data center and telecommunication) to smallscale systems (personal, portable/wearable, and automotive). This paper identifies drivers for progress and immediate and future challenges based on discussions at the 3rd Workshop on Thermal Management in Telecommunication Systems and Data Centers held in Redwood City, CA, USA, on November 4–5, 2015. Participants in this workshop represented industry and academia, with backgrounds ranging from data center thermal management and energy efficiency to high-performance computing and liquid cooling, thermal management in wearable and mobile devices, and acoustic noise management. By considering a wide range of electronics cooling applications with different lengths and time scales, this paper identifies both common themes and diverging views in the thermal management community

Multiphysics modeling and simulation for large-scale integrated circuits

This dissertation is a process of seeking solutions to two important and challenging problems related to the design of modern integrated circuits (ICs): the ever increasing couplings among the multiphysics and the large problem size arising from the escalating complexity of the designs. A multiphysics-based computer-aided design methodology is proposed and realized to address multiple aspects of a design simultaneously, which include electromagnetics, heat transfer, fluid dynamics, and structure mechanics. The multiphysics simulation is based on the finite element method for its unmatched capabilities in handling complicate geometries and material properties. The capability of the multiphysics simulation is demonstrated through its applications in a variety of important problems, including the static and dynamic IR-drop analyses of power distribution networks, the thermal-ware high-frequency characterization of through-silicon-via structures, the full-wave electromagnetic analysis of high-power RF/microwave circuits, the modeling and analysis of three-dimensional ICs with integrated microchannel cooling, the characterization of micro- and nanoscale electrical-mechanical systems, and the modeling of decoupling capacitor derating in the power integrity simulations. To perform the large-scale analysis in a highly efficient manner, a domain decomposition scheme, parallel computing, and an adaptive time-stepping scheme are incorporated into the proposed multiphysics simulation. Significant reduction in computation time is achieved through the two numerical schemes and the parallel computing with multiple processors

Melting performance enhancement of thermal storage system by utilizing shape and position of double fin

In present study, a 2D rectangular enclosure was considered as a latent thermal energy storage (LTES) system. Lauric acid was used as PCM material. The aim of this study was to use fins to enhance melting process of PCM. Position and shape of double fins were considered as investigating parameters. At first stage three different positions were considered for fins of rectangular shape. Results indicated that amongst aforementioned cases, best results were achieved when double fins were located at lower half of enclosure. Results revealed that up to 1800s could be saved during whole melting process. At second step, two trapezoidal form and one triangular shaped double fins were used to evaluate the effect of fin shape. In these cases, fins were placed at optimum position concluded from previous stage. Results presented that up to Fo = 0.15, best values of Nusselt numbers were related to triangular shaped fins. After Fo = 0.15, the case with triangular fin has least Nu number. The best melting performance was related to triangular fins at which 1000s less melting time was observed. Enhancement ratio results presented better performance for triangular fins after second of 2500

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Modeling the SAC microstructure evolution under thermal, thermomechanical and electrical constraints

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Remote Powering and Communication of Implantable Biosensors Through Inductive Link

Nowadays there is an increasing interest in the field of implantable biosensors. The possibility of real-time monitoring of the human body from inside paves the way to a large number of applications and offers wide opportunities for the future. Within this scenario, the i-IronIC project aims to develop an implantable, low cost, health-care device for real-time monitoring of human metabolites. The contribution of this research work to the i-IronIC project consists of the design and realization of a complete platform to provide power, data communication and remote control to the implantable biosensor. High wearability of the transmitting unit, low invasivity of the implanted electronics, integration of the power management module within the sensor, and a reliable communication protocol with portable devices are the key points of this platform. The power is transmitted to the implanted sensor by exploiting an inductive link. Simulations have been performed to check the effects of several variables on the link performance. These simulations have finally confirmed the possibility to operate in the low megahertz range, where tissue absorption is minimum, even if a miniaturized receiving inductor is used. A wearable patch has been designed to transmit power through the body tissues by driving an external inductor. The same inductive link is used to achieve bidirectional data communication with the implanted device. The patch, named IronIC, is powered by lithium-ion polymer batteries and can be remotely controlled by means of a dedicated Android application running on smartphones and tablets. Long-range communication between the patch and portable devices is performed by means of Bluetooth protocol. Different typologies of receiving inductors have been designed to minimize the size of the implantable device and reduce the discomfort of the patience. Multi-layer, printed spiral inductors and microfabricated spiral inductors have been designed, fabricated and tested. Both the approaches involve a sensibly smaller size, as compared to classic “pancake” inductors used for remote powering. Furthermore, the second solution enables the realization of the receiving inductor directly on the silicon substrate hosting the sensor, thus involving a further miniaturization of the implanted device. An integrated power module has been designed and fabricated in 0.18 μm CMOS technology to perform power management and data communication with the external patch. The circuit, to be merged with the sensor readout circuit, consists of an half-wave voltage rectifier, a low-dropout regulator, an amplitude demodulator and a load modulator. The module receives the power from the implanted inductor and provides a stable voltage to the sensor readout circuit. Finally, the amplitude demodulator and the load modulator enable short-range communication with the patch

Characterization of Nanomaterials: Selected Papers from 6th Dresden Nanoanalysis Symposiumc

This Special Issue “Characterization of Nanomaterials” collects nine selected papers presented at the 6th Dresden Nanoanalysis Symposium, held at Fraunhofer Institute for Ceramic Technologies and Systems in Dresden, Germany, on 31 August 2018. Following the specific motto of this annual symposium “Materials challenges—Micro- and nanoscale characterization”, it covered various topics of nanoscale materials characterization along the whole value and innovation chain, from fundamental research up to industrial applications. The scope of this Special Issue is to provide an overview of the current status, recent developments and research activities in the field of nanoscale materials characterization, with a particular emphasis on future scenarios. Primarily, analytical techniques for the characterization of thin films and nanostructures are discussed, including modeling and simulation. We anticipate that this Special Issue will be accessible to a wide audience, as it explores not only methodical aspects of nanoscale materials characterization, but also materials synthesis, fabrication of devices and applications

Ultra-thin silicon technology for tactile sensors

In order to meet the requirements of high performance flexible electronics in fast growing portable consumer electronics, robotics and new fields such as Internet of Things (IoT), new techniques such as electronics based on nanostructures, molecular electronics and quantum electronics have emerged recently. The importance given to the silicon chips with thickness below 50 μm is particularly interesting as this will advance the 3D IC technology as well as open new directions for high-performance flexible electronics. This doctoral thesis focusses on the development of silicon–based ultra-thin chip (UTC) for the next generation flexible electronics. UTCs, on one hand can provide processing speed at par with state-of-the-art CMOS technology, and on the other provide the mechanical flexibility to allow smooth integration on flexible substrates. These development form the motivation behind the work presented in this thesis. As the thickness of any silicon piece decreases, the flexural rigidity decreases. The flexural rigidity is defined as the force couple required to bend a non-rigid structure to a unit curvature, and therefore the flexibility increases. The new approach presented in this thesis for achieving thin silicon exploits existing and well-established silicon infrastructure, process, and design modules. The thin chips of thicknesses ranging between 15 μm – 30 μm, were obtained from processed bulk wafer using anisotropic chemical etching. The thesis also presents thin wafer transfer using two-step transfer printing approach, packaging by lamination or encapsulation between two flexible layerand methods to get the electrical connections out of the chip. The devices realised on the wafer as part of front-end processing, consisted capacitors and transistors, have been tested to analyse the effect of bending on the electrical characteristics. The capacitance of metal-oxide-semiconductor (MOS) capacitors increases by ~5% during bending and similar shift is observed in flatband and threshold voltages. Similarly, the carrier mobility in the channel region of metal-oxide-semiconductor field effect transistor (MOSFET) increases by 9% in tensile bending and decreases by ~5% in compressive bending. The analytical model developed to capture the effect of banding on device performance showed close matching with the experimental results. In order to employ these devices as tactile sensors, two types of piezoelectric materials are investigated, and used in extended gate configuration with the MOSFET. Firstly, a nanocomposite of Poly(vinylidene fluoride-co-trifluoroethylene), P(VDF-TrFE) and barium titanate (BT) was developed. The composite, due to opposite piezo and pyroelectric coefficients of constituents, was able to suppress the sensitivity towards temperature when force and temperature varied together, The sensitivity to force in extended gate configuration was measured to be 630 mV/N, and sensitivity to temperature was 6.57 mV/oC, when it was varied during force application. The process optimisation for sputtering piezoelectric Aluminium Nitride (AlN) was also carried out with many parametric variation. AlN does not require poling to exhibit piezoelectricity and therefore offers an attractive alternative for the piezoelectric layer used in devices such as POSFET (where piezoelectric material is directly deposited over the gate area of MOSFET). The optimised process gave highly orientated columnar structure AlN with piezoelectric coefficient of 5.9 pC/N and when connected in extended gate configuration, a sensitivity (normalised change in drain current per unit force) of 2.65 N-1 was obtained