Framework of Hardware Trojan Detection Leveraging Structural Checking Tool

Since there is a significant demand for obtaining third-party soft Intellectual Property (IP) by first-party integrated circuit (IC) vendors, it is becoming easier for adversaries to insert malicious logic known as hardware Trojans into designs. Due to this, vendors need to find ways to screen the third-party IPs for possible security threats and then mitigate them. The development of the Structural Checking (SC) tool provides a solution to this issue. This tool analyzes the structure of an unknown soft IP design and creates a network of all the signals within the design and how they are connected to each other. In addition, these signals will be assigned with assets. Assets describe the central role of a signal in the entire design. These assets are then used to create asset patterns, which will be crucial for this thesis research. Previous research on SC tool focuses on Trojan detection by comparing and matching an unknown design to a trusted design in a Golden Reference Library. In this thesis research, another method of Trojan detection has been implemented in the SC tool, which focuses on recognizing specific asset patterns that mainly exist in Trojan-infested designs. These specific asset patterns can then be used to check against unknown designs for Trojans without using a Golden Reference Library. This thesis improves this method by creating a new framework for easily identifying the unique Trojan asset patterns

Reliable Design Versus Trust

This presentation focuses on reliability and trust for the users portion of the FPGA design flow. It is assumed that the manufacturer prior to hand-off to the user tests FPGA internal components. The objective is to present the challenges of creating reliable and trusted designs. The following will be addressed: What makes a design vulnerable to functional flaws (reliability) or attackers (trust)? What are the challenges for verifying a reliable design versus a trusted design