151,916 research outputs found
Fast Power and Energy Efficiency Analysis of FPGA-based Wireless Base-band Processing
Nowadays, demands for high performance keep on increasing in the wireless
communication domain. This leads to a consistent rise of the complexity and
designing such systems has become a challenging task. In this context, energy
efficiency is considered as a key topic, especially for embedded systems in
which design space is often very constrained. In this paper, a fast and
accurate power estimation approach for FPGA-based hardware systems is applied
to a typical wireless communication system. It aims at providing power
estimates of complete systems prior to their implementations. This is made
possible by using a dedicated library of high-level models that are
representative of hardware IPs. Based on high-level simulations, design space
exploration is made a lot faster and easier. The definition of a scenario and
the monitoring of IP's time-activities facilitate the comparison of several
domain-specific systems. The proposed approach and its benefits are
demonstrated through a typical use case in the wireless communication domain.Comment: Presented at HIP3ES, 201
Modeling and visualizing networked multi-core embedded software energy consumption
In this report we present a network-level multi-core energy model and a
software development process workflow that allows software developers to
estimate the energy consumption of multi-core embedded programs. This work
focuses on a high performance, cache-less and timing predictable embedded
processor architecture, XS1. Prior modelling work is improved to increase
accuracy, then extended to be parametric with respect to voltage and frequency
scaling (VFS) and then integrated into a larger scale model of a network of
interconnected cores. The modelling is supported by enhancements to an open
source instruction set simulator to provide the first network timing aware
simulations of the target architecture. Simulation based modelling techniques
are combined with methods of results presentation to demonstrate how such work
can be integrated into a software developer's workflow, enabling the developer
to make informed, energy aware coding decisions. A set of single-,
multi-threaded and multi-core benchmarks are used to exercise and evaluate the
models and provide use case examples for how results can be presented and
interpreted. The models all yield accuracy within an average +/-5 % error
margin
Building Blocks for Control System Software
Software implementation of control laws for industrial systems seem straightforward, but is not. The computer code stemming from the control laws is mostly not more than 10 to 30% of the total. A building-block approach for embedded control system development is advocated to enable a fast and efficient software design process.\ud
We have developed the CTJ library, Communicating Threads for Java¿,\ud
resulting in fundamental elements for creating building blocks to implement communication using channels. Due to the simulate-ability, our building block method is suitable for a concurrent engineering design approach. Furthermore, via a stepwise refinement process, using verification by simulation, the implementation trajectory can be done efficiently
The TASTE Toolset: turning human designed heterogeneous systems into computer built homogeneous software.
The TASTE tool-set results from spin-off studies of the ASSERT project, which started in 2004 with the objective to propose innovative and pragmatic solutions to develop real-time software. One of the primary targets was satellite flight software, but it appeared quickly that their characteristics were shared among various embedded systems. The solutions that we developed now comprise a process and several tools ; the development process is based on the idea that real-time, embedded systems are heterogeneous by nature and that a unique UML-like language was not helping neither their construction, nor their validation. Rather than inventing yet another "ultimate" language, TASTE makes the link between existing and mature technologies such as Simulink, SDL, ASN.1, C, Ada, and generates complete, homogeneous software-based systems that one can straightforwardly download and execute on a physical target. Our current prototype is moving toward a marketed product, and sequel studies are already in place to support, among others, FPGA systems
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