6 research outputs found
Recommended from our members
Layer assignment and routing optimization for advanced technologies
As VLSI technology scales to deep sub-micron and beyond, it becomes
increasingly challenging to achieve timing closure for VLSI design. Since a
complete design flow consists of several phases, such as logic synthesis, placement, and routing, interconnect synthesis plays an important role which includes buffer insertion/sizing and timing-driven routing. Although progress has been achieved by many advanced routing techniques, the following aspects
can be exploited sufficiently for further improvement: (1) incremental layer assignment for timing optimization; (2) signal routing with the requirement of regularity; (3) power-efficient optical-electrical interconnect paradigm. Thus, to perform the layer assignment and routing optimization for advanced technologies,
an automated routing engine in a global view is essential to benefit the interconnect design while satisfying specific requirements.
This dissertation proposes a set of algorithms and methodology on layer
assignment and routing optimization for advanced technologies. The research includes two timing-driven incremental layer assignment approaches, synergistic
topology generation and routing synthesis for signal groups, and optical-electrical routing design for power efficiency.
For incremental layer assignment, most of the conventional approaches
target via minimization but neglect the timing issues. Meanwhile, via delays
are ignored but should be considered in emerging technology nodes. Then two
timing-driven incremental layer assignment frameworks are proposed, where all the nets are solved simultaneously with the integration of via delays: (1) optimization of the total sum of net delays and reduction of slew violations; (2) minimization of critical path timing in selected nets.
For on-chip signal routing, the bundled bits in one group may have different
pin locations, but they have to be routed in a regular manner by sharing common topologies. Very few previous works target inter-bit regularity via multi-layer topology selection. Furthermore, the routability and wire-length of the signal bits should also be optimized. Then an advanced synergistic routing engine is promoted, which is able to not only control routability and wire-length but also guide each bit routing intelligently for design regularity.
For optical-electrical co-design routing, optical interconnect shows its
advantage due to the dominance of bandwidth-distance-power properties. The previous works lack a detailed exploration of optical-electrical co-design for on-chip interconnects. During the transmission, signal quality can be affected by various loss sources and Electrical to Optical (EO)/Optical to Electrical (OE) conversion overheads should also be considered. Then a power-efficient routing flow for on-chip signals is presented, where optical connections can collaborate with electrical wires seamlessly.
The effectiveness of proposed algorithms and techniques is demonstrated in this dissertation. These approaches are able to achieve the improvements regarding specific metrics and eventually benefit the routing flow.Electrical and Computer Engineerin
Interconnect Planning for Physical Design of 3D Integrated Circuits
Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation.
This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning.
A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation.:1 Introduction
1.1 The 3D Integration Approach for Electronic Circuits
1.2 Technologies for 3D Integrated Circuits
1.3 Design Approaches for 3D Integrated Circuits
2 State of the Art in Design Automation for 3D Integrated Circuits
2.1 Thermal Management
2.2 Partitioning and Floorplanning
2.3 Placement and Routing
2.4 Power and Clock Delivery
2.5 Design Challenges
3 Research Objectives
4 Planning Through-Silicon Via Islands for Block-Level Design Reuse
4.1 Problems for Design Reuse in 3D Integrated Circuits
4.2 Connecting Blocks Using Through-Silicon Via Islands
4.2.1 Problem Formulation and Methodology Overview
4.2.2 Net Clustering
4.2.3 Insertion of Through-Silicon Via Islands
4.2.4 Deadspace Insertion and Redistribution
4.3 Experimental Investigation
4.3.1 Wirelength Estimation
4.3.2 Configuration
4.3.3 Results and Discussion
4.4 Summary and Conclusions
5 Planning Through-Silicon Vias for Design Optimization
5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias
5.2 Multiobjective Design Optimization of 3D Integrated Circuits
5.2.1 Methodology Overview and Configuration
5.2.2 Techniques for Deadspace Optimization
5.2.3 Design-Quality Analysis
5.2.4 Planning Different Types of Through-Silicon Vias
5.3 Experimental Investigation
5.3.1 Configuration
5.3.2 Results and Discussion
5.4 Summary and Conclusions
6 3D Floorplanning for Structural Planning of Massive Interconnects
6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits
6.2 Corner Block List Extended for Block Alignment
6.2.1 Alignment Encoding
6.2.2 Layout Generation: Block Placement and Alignment
6.3 3D Floorplanning Methodology
6.3.1 Optimization Criteria and Phases and Related Cost Models
6.3.2 Fast Thermal Analysis
6.3.3 Layout Operations
6.3.4 Adaptive Optimization Schedule
6.4 Experimental Investigation
6.4.1 Configuration
6.4.2 Results and Discussion
6.5 Summary and Conclusions
7 Research Summary, Conclusions, and Outlook
Dissertation Theses
Notation
Glossary
BibliographyDreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück.
In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase.
Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich.:1 Introduction
1.1 The 3D Integration Approach for Electronic Circuits
1.2 Technologies for 3D Integrated Circuits
1.3 Design Approaches for 3D Integrated Circuits
2 State of the Art in Design Automation for 3D Integrated Circuits
2.1 Thermal Management
2.2 Partitioning and Floorplanning
2.3 Placement and Routing
2.4 Power and Clock Delivery
2.5 Design Challenges
3 Research Objectives
4 Planning Through-Silicon Via Islands for Block-Level Design Reuse
4.1 Problems for Design Reuse in 3D Integrated Circuits
4.2 Connecting Blocks Using Through-Silicon Via Islands
4.2.1 Problem Formulation and Methodology Overview
4.2.2 Net Clustering
4.2.3 Insertion of Through-Silicon Via Islands
4.2.4 Deadspace Insertion and Redistribution
4.3 Experimental Investigation
4.3.1 Wirelength Estimation
4.3.2 Configuration
4.3.3 Results and Discussion
4.4 Summary and Conclusions
5 Planning Through-Silicon Vias for Design Optimization
5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias
5.2 Multiobjective Design Optimization of 3D Integrated Circuits
5.2.1 Methodology Overview and Configuration
5.2.2 Techniques for Deadspace Optimization
5.2.3 Design-Quality Analysis
5.2.4 Planning Different Types of Through-Silicon Vias
5.3 Experimental Investigation
5.3.1 Configuration
5.3.2 Results and Discussion
5.4 Summary and Conclusions
6 3D Floorplanning for Structural Planning of Massive Interconnects
6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits
6.2 Corner Block List Extended for Block Alignment
6.2.1 Alignment Encoding
6.2.2 Layout Generation: Block Placement and Alignment
6.3 3D Floorplanning Methodology
6.3.1 Optimization Criteria and Phases and Related Cost Models
6.3.2 Fast Thermal Analysis
6.3.3 Layout Operations
6.3.4 Adaptive Optimization Schedule
6.4 Experimental Investigation
6.4.1 Configuration
6.4.2 Results and Discussion
6.5 Summary and Conclusions
7 Research Summary, Conclusions, and Outlook
Dissertation Theses
Notation
Glossary
Bibliograph
Fixed-outline bus-driven floorplanning.
Jiang, Yan.Thesis (M.Phil.)--Chinese University of Hong Kong, 2011.Includes bibliographical references (p. 87-92).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Physical Design --- p.2Chapter 1.2 --- Floorplanning --- p.6Chapter 1.2.1 --- Floorplanning Objectives --- p.7Chapter 1.2.2 --- Common Approaches --- p.8Chapter 1.3 --- Motivations and Contributions --- p.14Chapter 1.4 --- Organization of the Thesis --- p.15Chapter 2 --- Literature Review on BDF --- p.17Chapter 2.1 --- Zero-Bend BDF --- p.17Chapter 2.1.1 --- BDF Using the Sequence-Pair Representation --- p.17Chapter 2.1.2 --- Using B*-Tree and Fast SA --- p.20Chapter 2.2 --- Two-Bend BDF --- p.22Chapter 2.3 --- TCG-Based Multi-Bend BDF --- p.25Chapter 2.3.1 --- Placement Constraints for Bus --- p.26Chapter 2.3.2 --- Bus Ordering --- p.28Chapter 2.4 --- Bus-Pin-Aware BDF --- p.30Chapter 2.5 --- Summary --- p.33Chapter 3 --- Fixed-Outline BDF --- p.35Chapter 3.1 --- Introduction --- p.35Chapter 3.2 --- Problem Formulation --- p.36Chapter 3.3 --- The Overview of Our Approach --- p.36Chapter 3.4 --- Partitioning --- p.37Chapter 3.4.1. --- The Overview of Partitioning --- p.38Chapter 3.4.2 --- Building a Hypergraph G --- p.39Chapter 3.5 --- Floorplaiining with Bus Routing --- p.43Chapter 3.5.1 --- Find Bus Routes --- p.43Chapter 3.5.2 --- Realization of Bus Routes --- p.48Chapter 3.5.3 --- Details of the Annealing Process --- p.50Chapter 3.6 --- Handle Fixed-Outline Constraints --- p.52Chapter 3.7 --- Bus Layout --- p.52Chapter 3.8 --- Experimental Results --- p.56Chapter 3.9 --- Summary --- p.61Chapter 4 --- Fixed-Outline BDF with L-shape bus --- p.63Chapter 4.1 --- Introduction --- p.63Chapter 4.2 --- Problem Formulation --- p.64Chapter 4.3 --- Our Approach --- p.65Chapter 4.3.1 --- Bus Routability Checking --- p.67Chapter 4.3.2 --- Details of the Annealing Process --- p.79Chapter 4.4 --- Experimental Results --- p.79Chapter 4.5 --- Summary --- p.82Chapter 5 --- Conclusion --- p.85Bibliography --- p.9
Transitive closure graph based multi-bend bus driven floorplanning
Ma, Tilen.Thesis (M.Phil.)--Chinese University of Hong Kong, 2007.Includes bibliographical references (leaves 98-100).Abstracts in English and Chinese.Abstract --- p.iChapter 0.1 --- Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Physical Design Cycle --- p.2Chapter 1.2 --- Floorplanning --- p.6Chapter 1.2.1 --- Floorplanning Objectives --- p.7Chapter 1.2.2 --- Common Approaches --- p.8Chapter 1.3 --- Motivations and Contributions --- p.11Chapter 1.4 --- Organization of the Thesis --- p.13Chapter 2 --- Literature Review on Placement Constraints in Floorplanning --- p.15Chapter 2.1 --- Introduction --- p.15Chapter 2.2 --- Algorithms for Abutment Constraint --- p.16Chapter 2.3 --- Algorithms for Alignment Constraint --- p.18Chapter 2.4 --- Algorithms for Boundary Constraint --- p.20Chapter 2.5 --- Unified Approach for Placement Constraints --- p.23Chapter 2.5.1 --- Representation of Placement Constraints --- p.23Chapter 2.5.2 --- Handling Relative Placement Constraints --- p.24Chapter 2.5.3 --- Examples for Handling Placement Constraints --- p.25Chapter 3 --- Literature Review on Bus-Driven Floorplanning --- p.28Chapter 3.1 --- Introduction --- p.28Chapter 3.2 --- Previous Work --- p.28Chapter 3.2.1 --- Zero-Bend Bus-Driven Floorplanning [3] --- p.28Chapter 3.2.2 --- Two-Bend Bus-Driven Floorplanning [1] --- p.32Chapter 4 --- Placement Constraints for Multi-Bend Bus in TCGs --- p.38Chapter 4.1 --- Introduction --- p.38Chapter 4.2 --- Transitive Closure Graph [6] --- p.39Chapter 4.3 --- Placement Constraints for Zero-Bend Bus --- p.41Chapter 4.4 --- Placement Constraints for Multi-Bend Bus --- p.44Chapter 4.5 --- Placement Constraints for Bus Ordering --- p.45Chapter 4.5.1 --- Natural Bus Ordering in TCGs --- p.45Chapter 4.5.2 --- Explicit Bus Ordering in TCGs --- p.46Chapter 5 --- TCG-Based Bus-Driven Floorplanning --- p.48Chapter 5.1 --- Motivation --- p.48Chapter 5.2 --- Problem Formulation --- p.49Chapter 5.3 --- Methodology --- p.50Chapter 5.3.1 --- Construction of Reduced Graphs --- p.51Chapter 5.3.2 --- Construction of Common Graph --- p.52Chapter 5.3.3 --- Spanning Tree for Bus Assignment --- p.53Chapter 5.3.4 --- Formation of Bus Components --- p.55Chapter 5.3.5 --- Bus Feasibility Check --- p.56Chapter 5.3.6 --- Overlap Removal --- p.57Chapter 5.3.7 --- Floorplan Realization --- p.58Chapter 5.3.8 --- Simulated Annealing --- p.58Chapter 5.3.9 --- Soft Module Adjustment --- p.60Chapter 5.4 --- Experimental Results --- p.60Chapter 5.5 --- Summary --- p.65Chapter 6 --- Conclusion --- p.67Chapter A --- Appendix --- p.69Chapter A.1 --- Well-Known Algorithms --- p.69Chapter A.1.1 --- Kruskal's Algorithm --- p.69Chapter A.1.2 --- Bellman-Ford Algorithm --- p.69Chapter A.2 --- Figures of Resulting Floorplans --- p.71Chapter A.2.1 --- Data Set One --- p.71Chapter A.2.2 --- Data Set Two --- p.80Chapter A.2.3 --- Data Set Three --- p.85Chapter A.2.4 --- Data Set Four --- p.92Bibliography --- p.9
Bus-driven floorplanning.
Law Hoi Ying.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 101-106).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- VLSI Design Cycle --- p.2Chapter 1.2 --- Physical Design Cycle --- p.6Chapter 1.3 --- Floorplanning --- p.10Chapter 1.3.1 --- Floorplanning Objectives --- p.11Chapter 1.3.2 --- Common Approaches --- p.12Chapter 1.3.3 --- Interconnect-Driven Floorplanning --- p.14Chapter 1.4 --- Motivations and Contributions --- p.15Chapter 1.5 --- Organization of the Thesis --- p.17Chapter 2 --- Literature Review on 2D Floorplan Representations --- p.18Chapter 2.1 --- Types of Floorplans --- p.18Chapter 2.2 --- Floorplan Representations --- p.20Chapter 2.2.1 --- Slicing Floorplan --- p.21Chapter 2.2.2 --- Non-slicing Floorplan --- p.22Chapter 2.2.3 --- Mosaic Floorplan --- p.30Chapter 2.3 --- Summary --- p.35Chapter 3 --- Literature Review on 3D Floorplan Representations --- p.37Chapter 3.1 --- Introduction --- p.37Chapter 3.2 --- Problem Formulation --- p.38Chapter 3.3 --- Previous Work --- p.38Chapter 3.4 --- Summary --- p.42Chapter 4 --- Literature Review on Bus-Driven Floorplanning --- p.44Chapter 4.1 --- Problem Formulation --- p.44Chapter 4.2 --- Previous Work --- p.45Chapter 4.2.1 --- Abutment Constraint --- p.45Chapter 4.2.2 --- Alignment Constraint --- p.49Chapter 4.2.3 --- Bus-Driven Floorplanning --- p.52Chapter 4.3 --- Summary --- p.53Chapter 5 --- Multi-Bend Bus-Driven Floorplanning --- p.55Chapter 5.1 --- Introduction --- p.55Chapter 5.2 --- Problem Formulation --- p.56Chapter 5.3 --- Methodology --- p.57Chapter 5.3.1 --- Shape Validation --- p.58Chapter 5.3.2 --- Bus Ordering --- p.65Chapter 5.3.3 --- Floorplan Realization --- p.72Chapter 5.3.4 --- Simulated Annealing --- p.73Chapter 5.3.5 --- Soft Block Adjustment --- p.75Chapter 5.4 --- Experimental Results --- p.75Chapter 5.5 --- Summary --- p.77Chapter 6 --- Bus-Driven Floorplanning for 3D Chips --- p.80Chapter 6.1 --- Introduction --- p.80Chapter 6.2 --- Problem Formulation --- p.81Chapter 6.3 --- The Representation --- p.82Chapter 6.3.1 --- Overview --- p.82Chapter 6.3.2 --- Review of TCG --- p.83Chapter 6.3.3 --- Layered Transitive Closure Graph (LTCG) --- p.84Chapter 6.3.4 --- Aligning Blocks --- p.85Chapter 6.3.5 --- Solution Perturbation --- p.87Chapter 6.4 --- Simulated Annealing --- p.92Chapter 6.5 --- Soft Block Adjustment --- p.92Chapter 6.6 --- Experimental Results --- p.93Chapter 6.7 --- Summary --- p.94Chapter 6.8 --- Acknowledgement --- p.95Chapter 7 --- Conclusion --- p.99Bibliography --- p.10