Low-temperature amorphous oxide semiconductors for thin-film transistors and memristors: physical insights and applications

While amorphous oxides semiconductors (AOS), namely InGaZnO (IGZO), have found market application in the display industry, their disruptive properties permit to envisage for more advanced concepts such as System-on-Panel (SoP) in which AOS devices could be used for addressing (and readout) of sensors and displays, for communication, and even for memory as oxide memristors are candidates for the next-generation memories. This work concerns the application of AOS for these applications considering the low thermal budgets (< 180 °C) required for flexible, low cost and alternative substrates. For maintaining low driving voltages, a sputtered multicomponent/multi-layered high-κ dielectric (Ta2O5+SiO2) was developed for low temperature IGZO TFTs which permitted high performance without sacrificing reliability and stability. Devices’ performance under temperature was investigated and the bias and temperature dependent mobility was modelled and included in TCAD simulation. Even for IGZO compositions yielding very high thermal activation, circuit topologies for counteracting both this and the bias stress effect were suggested. Channel length scaling of the devices was investigated, showing that operation for radio frequency identification (RFID) can be achieved without significant performance deterioration from short channel effects, which are attenuated by the high-κ dielectric, as is shown in TCAD simulation. The applicability of these devices in SoP is then exemplified by suggesting a large area flexible radiation sensing system with on-chip clock-generation, sensor matrix addressing and signal read-out, performed by the IGZO TFTs. Application for paper electronics was also shown, in which TCAD simulation was used to investigate on the unconventional floating gate structure. AOS memristors are also presented, with two distinct operation modes that could be envisaged for data storage or for synaptic applications. Employing typical TFT methodologies and materials, these are ease to integrate in oxide SoP architectures

Interpretation and Regulation of Electronic Defects in IGZO TFTs Through Materials & Processes

The recent rise in the market for consumer electronics has fueled extensive research in the field of display. Thin-Film Transistors (TFTs) are used as active matrix switching devices for flat panel displays such as LCD and OLED. The following investigation involves an amorphous metal-oxide semiconductor that has the potential for improved performance over current technology, while maintaining high manufacturability. Indium-Gallium-Zinc-Oxide (IGZO) is a semiconductor material which is at the onset of commercialization. The low-temperature large-area deposition compatibility of IGZO makes it an attractive technology from a manufacturing standpoint, with an electron mobility that is 10 times higher than current amorphous silicon technology. The stability of IGZO TFTs continues to be a challenge due to the presence of defect states and problems associated with interface passivation. The goal of this dissertation is to further the understanding of the role of defect states in IGZO, and investigate materials and processes needed to regulate defects to the level at which the associated influence on device operation is controlled. The relationships between processes associated with IGZO TFT operation including IGZO sputter deposition, annealing conditions and back-channel passivation are established through process experimentation, materials analysis, electrical characterization, and modeling of electronic properties and transistor behavior. Each of these components has been essential in formulating and testing several hypotheses on the mechanisms involved, and directing efforts towards achieving the goal. Key accomplishments and quantified results are summarized as follows: • XPS analysis identified differences in oxygen vacancies in samples before and after oxidizing ambient annealing at 400 °C, showing a drop in relative integrated area of the O 1s peak from 32% to 19%, which experimentally translates to over a thousand fold decrease in the channel free electron concentration. • Transport behavior at cryogenic temperatures identified variable range hopping as the electron transport mechanism at temperature below 130 K, whereas at temperature greater than 130 K, the current vs temperature response followed an Arrhenius relationship consistent with extended state transport. • Refinement of an IGZO material model for TCAD simulation, which consists of oxygen vacancy donors providing an integrated space charge concentration NVO = +5e15 cm-3, and acceptor-like band-tail states with a total integrated ionized concentration of NTA = -2e18 cm-3. An intrinsic electron mobility was established to be Un = 12.7 cm2/V∙s. • A SPICE-compatible 2D on-state operation model for IGZO TFTs has been developed which includes the integration of drain-impressed deionization of band-tail states and results in a 2D modification of free channel charge. The model provides an exceptional match to measured data and TCAD simulation, with model parameters for channel mobility (Uch = 12 cm2/V∙s) and threshold voltage (VT = 0.14 V) having a close match to TCAD analogs. • TCAD material and device models for bottom-gate and double-gate TFT configurations have been developed which depict the role of defect states on device operation, as well as provide insight and support of a presented hypothesis on DIBL like device behavior associated with back-channel interface trap inhomogeneity. This phenomenon has been named Trap Associated Barrier Lowering (TABL). • A process integration scheme has been developed that includes IGZO back-channel passivation with PECVD SiO2, furnace annealing in O2 at 400 °C, and a thin capping layer of alumina deposited via atomic layer deposition. This process supports device stability when subjected to negative and positive bias stress conditions, and thermal stability up to 140 °C. It also enables TFT operation at short channel lengths (Leff ~ 3 µm) with steep subthreshold characteristics (SS ~ 120 mV/dec). The details of these contributions in the interpretation and regulation of electronic defect states in IGZO TFTs is presented, along with the support of device characteristics that are among the best reported in the literature. Additional material on a complementary technology which utilizes flash-lamp annealing of amorphous silicon will also be described. Flash-Lamp Annealed Polycrystalline Silicon (FLAPS) has realized n-channel and p-channel TFTs with promising results, and may provide an option for future applications with the highest performance demands. IGZO is rapidly emerging as the candidate to replace a-Si:H and address the performance needs of display products produced by large panel manufacturing

On the Reversible Effects of Bias-Stress Applied to Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistors

The role of amorphous IGZO (Indium Gallium Zinc Oxide) in Thin Film Transistors (TFT) has found its application in emerging display technologies such as active matrix liquid crystal display (LCD) and active matrix organic light-emitting diode (AMOLED) due to factors such as high mobility 10-20 cm2/(V.s), low subthreshold swing (~120mV/dec), overall material stability and ease of fabrication. However, prolonged application of gate bias on the TFT results in deterioration of I-V characteristics such as sub-threshold distortion and a distinct shift in threshold voltage. Both positive-bias and negative-bias affects have been investigated. In most cases positive-stress was found to have negligible influence on device characteristics, however a stress induced trap state was evident in certain cases. Negative stress demonstrated a pronounced influence by donor like interface traps, with significant transfer characteristics shift that was reversible over a period of time at room temperature. It was also found that the reversible mechanism to pre-stress conditions was accelerated when samples were subjected to cryogenic temperature (77 K). To improve device performance BG devices were subjected to extended anneals and encapsulated with ALD alumina. These devices were found to have excellent resistance to bias stress. Double gate devices that were subjected to extended anneals and alumina capping revealed similar results with better electrostatics compared to BG devices. The cause and effect of bias stress and its reversible mechanisms on IGZO TFTs has been studied and explained with supporting models

Interpretation and Physical Modeling of Electronic Transport and Defect States in IGZO Thin-Film Transistors

This work is a comprehensive study on the interpretation and modeling of electronic transport behavior and defect states in indium-gallium-zinc-oxide (IGZO) TFTs. Key studies have focused on advancing the state of IGZO TFTs by addressing several challenges in device stability, scaling, and device modeling. These studies have provided new insight on the associated mechanisms and have resulted in the realization of scaled thin-film transistors that exhibit excellent electrical performance and stability. This work has demonstrated the ability to scale the conventional inverted staggered IGZO TFT down to one micron channel length, with excellent on-state and off-state performance where the VT ≈1 V, µeff =12 cm2/Vs, Ileak ≤ 10-12 A/µm and SS ≈ 160 mV/dec. The working source/drain electrodes are direct metal contact regions to the IGZO, which requires several microns of gate overlap to provide ohmic behavior with minimal series resistance and ensure tolerance to overlay error. New results utilizing ion implantation for self-aligned source/drain regions present a path towards submicron channel length. This strategy offers a reduction in channel length as well as parasitic capacitance, which translates to improvement in RC delay and associated voltage losses due to charge-sharing. The realization of self-aligned TFTs using boron ion implantation for selective activation was introduced in a first-time report of boron-doped IGZO. Cryogenic measurements made on long-channel devices has revealed temperature-dependent behavior that is not explained by existing TCAD models employed for defect states and carrier mobility. A completely new device model using Silvaco Atlas has been established which properly accounts for the role of donor-like oxygen vacancy defects, acceptor-like band-tail states, acceptor-like interface traps, and a temperature-dependent intrinsic channel mobility. The developed model demonstrates a remarkable match to transfer characteristics measured at T = 150 K to room temperature. A power-law fit for the µch = f(T) relationship, which resembles 〖μ ~ T〗^((+3)⁄2) behavior consistent with ionized defect scattering. The mobility model is expressly independent of carrier concentration, without dependence on the applied gate bias. The device model is consistent with a compact model developed for circuit simulation (SPICE) that has been recently refined to include on-state and off-state operation. While IGZO is the only AOS technology mature enough for commercialization, the effective electron channel mobility µeff ~ 10 cm2/Vs presents a performance limitation. Other candidate AOS materials which have higher reported channel mobility values have also been investigated; specifically, indium-tungsten-oxide (IWO) and indium-gallium-tin-oxide (ITGO). These investigations serve as preliminary studies; device characteristics support the claims of high channel mobility; however the influence of defect states clearly indicates the need for further process development. The advancements realized in IGZO TFTs in this work will serve as a foundation for these alternative AOS materials

Implant Activated Source/Drain Regions for Self-Aligned IGZO TFT

In this work, amorphous Indium Gallium Zinc Oxide (IGZO) TFTs with channel lengths scaled as small as L = 1 µm are presented which demonstrate excellent electrical characteristics, however the traditional metal-contact defined source/drain regions typically require several microns of gate overlap in order to provide ohmic behavior with minimal series resistance and ensure tolerance to overlay error. In addition, further scaling the channel length by simply reducing the source/drain metal gap is not feasible. The focus of this study is to investigate techniques to realize self-aligned (SA) IGZO TFTs that are not subject to gate-source/drain misalignment due to overlay error or process bias. Top gate (TG) co-planar and bottom gate (BG) staggered TFTs are fabricated using plasma immersion and ion implantation to selectively form conductive IGZO regions, with the channel region blocked by a gate-defined mask. Among the investigated treatments, oxygen plasma activation and ion implanted activation via 11B+ and 40Ar+ has been successfully demonstrated. Due to metal gate charging during ion implantation of SA-TG devices, the characteristics show a significant left-shift whereas SA-BG devices do not show this behavior. Electrical results suggest a defect-induced mechanism is involved with 40Ar+ implant activation of the S/D regions. However, 11B+ implant activation is attributed to the formation of an electrically active donor species involving chemical bonding. Both boron and argon demonstrate pronounced degradation in charge injection at higher dose treatments. Finally, a novel lithographic strategy which utilizes top-side flood exposure rather than a back-side through-glass exposure has also been explored, which would enable SA-BG devices on non-transparent substrates

Assessment of High Mobility Oxide Thin-Film Transistors

The trend towards higher resolution, faster refresh rate active-matrix liquid-crystal displays (AMLCDs) as well as the emergence of active-matrix organic light-emitting diode (AMOLED) displays is driving the demand for amorphous oxide semiconductor thin-film transistors (AOS TFTs) with higher mobility. A physics-based model for carrier transport in an amorphous semiconductor is developed to estimate the mobility limits of an AOS TFT to be 71 cm² V⁻¹s⁻¹. Only the effective mass and band tail state density need to be specified, relating to the disorder in the amorphous semiconductor. Three ways are identified to achieve a mobility higher than that of quaternary amorphous indium gallium zinc oxide (a-IGZO) with a cation ratio of 1:1:1. i) Quaternary systems with a higher indium ratio; ii) lower disorder ternary oxides (e.g., boron indium oxide); iii) dual active layer (DAL) TFTs. ITO-IGZO DAL TFTs are directly compared with a-IGZO TFTs. The ITO-IGZO DAL TFT exhibits significantly improved performance with mean mobility of 31 cm² V⁻¹s⁻¹, threshold voltage of -3.6 V, sub-threshold swing of 175 mV dec, minimal hysteresis, and good bias temperature stress stability. Technology computer aided design (TCAD) simulation is used to elucidate the density of states (DOS) of various types of AOS TFTs. A mapping technique is introduced to relate experimental transfer characteristics to the sub-bandgap DOS model.Keywords: Thin-Film Transistor, TCAD Simulation, Amorphous Oxide Semiconducto

Engineering SiO2 Passivated Indium-Gallium-Zinc-Oxide TFTs for Improvement in Channel Control

The performance of Indium Gallium Zinc Oxide (IGZO) Thin-Film Transistors (TFTs) has improved significantly in recent years; however, device stability still remains a significant issue. In bottom-gate TFTs a difficult challenge is the lack of gate control on the back-channel region, resulting in distortion in ID - VGS characteristics. In this work a bottom-gate TFT process was established using SiO2 as a back-channel passivation layer. The process was modified with options to implement TG (TG) and Double-Gate (DG) configurations. TFTs were fabricated utilizing a SiO2 layer deposited shortly after the IGZO sputter process, followed by an oxidizing ambient anneal treatment. The process supports a low-defect IGZO interface, with TG and DG configurations demonstrating improvements in channel control compared to a traditional bottom-gate TFT. Electrical characteristics from each process treatment and gate configuration where then compared. A SPICE level 2 compatible IGZO TFT model was developed, with extracted parameter values providing a quantitative measure of device operation. Measured characteristics were also used to develop arerefined material and device model for TCAD simulation

Analysis of the hump phenomenon and needle defect states formed by driving stress in the oxide semiconductor

The reduction in current ability accompanied by the hump phenomenon in oxide semiconductor thin-film transistors to which high DC voltages and AC drive voltages are applied has not been studied extensively, although it is a significant bottleneck in the manufacture of integrated circuits. Here, we report on the origin of the hump and current drop in reliability tests caused by the degradation in the oxide semiconductor during a circuit driving test. The hump phenomenon and current drop according to two different driving stresses were verified. Through a numerical computational simulation, we confirmed that this issue can be caused by an additional “needle”, a shallow (~0.2 eV) and narrow (&lt;0.1 eV), defect state near the conduction band minimum (CBM). This is also discussed in terms of the dual current path caused by leakage current in the channel edge. © 2019, The Author(s).1

Passivation of Amorphous Indium-Gallium-Zinc Oxide (IGZO) Thin-Film Transistors

Thin-film transistors (TFTs) with channel materials made out of hydrogenated amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) have been extensively investigated. Amorphous silicon continues to dominate the large-format display technology; however newer technologies demand a higher performance TFT which a-Si:H cannot deliver due to its low electron mobility, µn ~ 1 cm2/V*s. Metal-oxide materials such as Indium-Gallium-Zinc Oxide (IGZO) have demonstrated semiconductor properties, and are candidates to replace a Si:H for TFT backplane technologies. This work involves the fabrication and characterization of TFTs utilizing a-IGZO deposited by RF sputtering. An overview of the process details and results from recently fabricated IGZO TFTs following designed experiments are presented, followed by analysis of electrical results. The investigated process variables were the thickness of the IGZO channel material, passivation layer material, and annealing conditions. The use of electron-beam deposited Aluminum oxide (alumina or Al2O3) as back-channel passivation material resulted in improved device stability; however ID VG transfer characteristics revealed the influence of back-channel interface traps. Results indicate that an interaction effect between the annealing condition (time/temperature) and the IGZO thickness on the electrical behavior of alumina-passivated devices may be significant. A device model implementing fixed charge and donor-like interface traps that are consistent with oxygen vacancies (OV) resulted in a reasonable match to measured characteristics. Modified annealing conditions have resulted in a reduction of back-channel interface traps, with levels comparable to devices fabricated without the addition of passivation material