10,793 research outputs found

    Illicit

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    Prose by Chelsea Yedinak

    Harbinger and Cathedrals

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    Fiction by Elena DeCook and Photography by Richard Sh

    PIC 18F452 implementation of digital filters

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    This research hopes to explore the computational limits of the PIC18f452 chip by encompassing the designing and implementation of two types of filters for the PIC 18F452 microcontroller. The main purpose of this research is to implement a floating-point least mean square (LMS) error adaptive filter and its secondary goal is a fixed-point implementation of finite impulse response (FIR) filter. FIR filters are specified via a graphical user interface (GUI) and upon demand, optimized C-language code is generated for the popular CCS PIC C-Compiler. In is the intent of this research to learn whether FIR filters can be made computationally viable on the PIC18 chips, can they run stably with reliable and repeatable performance? What is the minimum execution time possible at the processing limits of the chip? And how is filter attenuation affected when taps are scaled down from floating-point to fixed point? The FIR filter code generation software developed during this study allows graphical specification, inspection of response curves. (Abstract shortened by UMI.)

    Improved decoder metrics for DS-CDMA in practical 3G systems

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    While 4G mobile networks have been deployed since 2008. In several of the more developed markets, 3G mobile networks are still growing with 3G having the largest market -in terms of number of users- by 2019. 3G networks are based on Direct- Sequence Code-Division Multiple-Access (DS-CDMA). DS-CDMA suffers mainly from the Multiple Access Interference (MAI) and fading. Multi-User Detectors (MUDs) and Error Correcting Codes (ECCs) are the primary means to combat MAI and fading. MUDs, however, suffer from high complexity, including most of sub-optimal algorithms. Hence, most commercial implementations still use conventional single-user matched filter detectors. This thesis proposes improved channel decoder metrics for enhancing uplink performance in 3G systems. The basic idea is to model the MAI as conditionally Gaussian, instead of Gaussian, conditioned on the users’ cross-correlations and/or the channel fading coefficients. The conditioning implies a time-dependent variance that provides enhanced reliability estimates at the decoder inputs. We derive improved log-likelihood ratios (ILLRs) for bit- and chip- asynchronous multipath fading channels. We show that while utilizing knowledge of all users’ code sequences for the ILLR metric is very complicated in chip-asynchronous reception, a simplified expression relying on truncated group delay results in negligible performance loss. We also derive an expression for the error probability using the standard Gaussian approximation for asynchronous channels for the widely used raised cosine pule shaping. Our study framework considers practical 3G systems, with finite interleaving, correlated multipath fading channel models, practical pulse shaping, and system parameters obtained from CDMA2000 standard. Our results show that for the fully practical cellular uplink channel, the performance advantage due to ILLRs is significant and approaches 3 dB

    Receiver algorithms that enable multi-mode baseband terminals

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    Low order channel estimation for CDMA systems

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    New approaches and algorithms are developed for the identification and estimation of low order models that represent multipath channel effects in Code Division Multiple Access (CDMA) communication systems. Based on these parsimonious channel models, low complexity receivers such as RAKE receivers are considered to exploit these propagation effects and enhance the system performance. We consider the scenario where multipath is frequency selective slowly fading and where the channel components including delays and attenuation coefficients are assumed to be constant over one or few signalling intervals. We model the channel as a long FIR-like filter (or a tapped delay line filter) with the number of taps related to the ratio between the channel delay-spread and the chip duration. Due to the high data rate of new CDMA systems, the channel length in terms of the chip duration will be very large. With classical channel estimation techniques this will result in poor estimates of many of the channel parameters where most of them are zero leading to a reduction in the system performance. Unlike classical techniques which estimate directly the channel response given the number of taps or given an estimate of the channel length, the proposed techniques in this work will firstly identify the significant multipath parameters using model selection techniques, then estimate these identified parameters. Statistical tests are proposed to determine whether or not each individual parameter is significant. A low complexity RAKE receiver is then considered based on estimates of these identified parameters only. The level of significance with which we will make this assertion will be controlled based on statistical tests such as multiple hypothesis tests. Frequency and time domain based approaches and model selection techniques are proposed to achieve the above proposed objectives.The frequency domain approach for parsimonious channel estimation results in an efficient implementation of RAKE receivers in DS-CDMA systems. In this approach, we consider a training based strategy and estimate the channel delays and attenuation using the averaged periodogram and modified time delay estimation techniques. We then use model selection techniques such as the sphericity test and multiple hypotheses tests based on F-Statistics to identify the model order and select the significant channel paths. Simulations show that for a pre-defined level of significance, the proposed technique correctly identifies the significant channel parameters and the parsimonious RAKE receiver shows improved statistical as well as computational performance over classical methods. The time domain approach is based on the Bootstrap which is appropriate for the case when the distribution of the test statistics required by the multiple hypothesis tests is unknown. In this approach we also use short training data and model the channel response as an FIR filter with unknown length. Model parameters are then estimated using low complexity algorithms in the time domain. Based on these estimates, bootstrap based multiple hypotheses tests are applied to identify the non-zero coefficients of the FIR filter. Simulation results demonstrate the power of this technique for RAKE receivers in unknown noise environments. Finally we propose adaptive blind channel estimation algorithms for CDMA systems. Using only the spreading code of the user of interest and the received data sequence, four different adaptive blind estimation algorithms are proposed to estimate the impulse response of frequency selective and frequency non-selective fading channels. Also the idea is based on minimum variance receiver techniques. Tracking of a frequency selective varying fading channel is also considered.A blind based hierarchical MDL model selection method is also proposed to select non-zero parameters of the channel response. Simulation results show that the proposed algorithms perform better than previously proposed algorithms. They have lower complexity and have a faster convergence rate. The proposed algorithms can also be applied to the design of adaptive blind channel estimation based RAKE receivers

    High-speed equalization and transmission in electrical interconnections

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    The relentless growth of data traffic and increasing digital signal processing capabilities of integrated circuits (IC) are demanding ever faster chip-to-chip / chip-to-module serial electrical interconnects. As data rates increase, the signal quality after transmission over printed circuit board (PCB) interconnections is severely impaired. Frequency-dependent loss and crosstalk noise lead to a reduced eye opening, a reduced signal-to-noise ratio and an increased inter-symbol interference (ISI). This, in turn, requires the use of improved signal processing or PCB materials, in order to overcome the bandwidth (BW) limitations and to improve signal integrity. By applying an optimal combination of equalizer and receiver electronics together with BW-efficient modulation schemes, the transmission rate over serial electrical interconnections can be pushed further. At the start of this research, most industrial backplane connectors, meeting the IEEE and OIF specifications such as manufactured by e.g. FCI or TE connectivity, had operational capabilities of up to 25 Gb/s. This research was mainly performed under the IWT ShortTrack project. The goal of this research was to increase the transmission speed over electrical backplanes up to 100 Gb/s per channel for next-generation telecom systems and data centers. This requirement greatly surpassed the state-ofthe-art reported in previous publications, considering e.g. 25 Gb/s duobinary and 42.8 Gb/s PAM-4 transmission over a low-loss Megtron 6 electrical backplane using off-line processing. The successful implementation of the integrated transmitter (TX) and receiver (RX) (1) , clearly shows the feasibility of single lane interconnections beyond 80 Gb/s and opens the potential of realizing industrial 100 Gb/s links using a recent IC technology process. Besides the advancement of the state-of-the-art in the field of high-speed transceivers and backplane transmission systems, which led to several academic publications, the output of this work also attracts a lot of attention from the industry, showing the potential to commercialize the developed chipset and technologies used in this research for various applications: not only in high-speed electrical transmission links, but also in high-speed opto-electronic communications such as access, active optical cables and optical backplanes. In this dissertation, the background of this research, an overview of this work and the thesis organization are illustrated in Chapter 1. In Chapter 2, a system level analysis is presented, showing that the channel losses are limiting the transmission speed over backplanes. In order to enhance the serial data rate over backplanes and to eliminate the signal degradation, several technologies are discussed, such as signal equalization and modulation techniques. First, a prototype backplane channel, from project partner FCI, implemented with improved backplane connectors is characterized. Second, an integrated transversal filter as a feed-forward equalizer (FFE) is selected to perform the signal equalization, based on a comprehensive consideration of the backplane channel performance, equalization capabilities, implementation complexity and overall power consumption. NRZ, duobinary and PAM-4 are the three most common modulation schemes for ultra-high speed electrical backplane communication. After a system-level simulation and comparison, the duobinary format is selected due to its high BW efficiency and reasonable circuit complexity. Last, different IC technology processes are compared and the ST microelectronics BiCMOS9MW process (featuring a fT value of over 200 GHz) is selected, based on a trade-off between speed and chip cost. Meanwhile it also has a benefit for providing an integrated microstrip model, which is utilized for the delay elements of the FFE. Chapter 3 illustrates the chip design of the high-speed backplane TX, consisting of a multiplexer (MUX) and a 5-tap FFE. The 4:1 MUX combines four lower rate streams into a high-speed differential NRZ signal up to 100 Gb/s as the FFE input. The 5-tap FFE is implemented with a novel topology for improved testability, such that the FFE performance can be individually characterized, in both frequency- and time-domain, which also helps to perform the coefficient optimization of the FFE. Different configurations for the gain cell in the FFE are compared. The gilbert configuration shows most advantages, in both a good high-frequency performance and an easy way to implement positive / negative amplification. The total chip, including the MUX and the FFE, consumes 750mW from a 2.5V supply and occupies an area of 4.4mm × 1.4 mm. In Chapter 4, the TX chip is demonstrated up to 84 Gb/s. First, the FFE performance is characterized in the frequency domain, showing that the FFE is able to work up to 84 Gb/s using duobinary formats. Second, the combination of the MUX and the FFE is tested. The equalized TX outputs are captured after different channels, for both NRZ and duobinary signaling at speeds from 64 Gb/s to 84 Gb/s. Then, by applying the duobinary RX 2, a serial electrical transmission link is demonstrated across a pair of 10 cm coax cables and across a 5 cm FX-2 differential stripline. The 5-tap FFE compensates a total loss between the TX and the RX chips of about 13.5 dB at the Nyquist frequency, while the RX receives the equalized signal and decodes the duobinary signal to 4 quarter rate NRZ streams. This shows a chip-to-chip data link with a bit error rate (BER) lower than 10−11. Last, the electrical data transmission between the TX and the RX over two commercial backplanes is demonstrated. An error-free, serial duobinary transmission across a commercial Megtron 6, 11.5 inch backplane is demonstrated at 48 Gb/s, which indicates that duobinary outperforms NRZ for attaining higher speed or longer reach backplane applications. Later on, using an ExaMAX® backplane demonstrator, duobinary transmission performance is verified and the maximum allowed channel loss at 40 Gb/s transmission is explored. The eye diagram and BER measurements over a backplane channel up to 26.25 inch are performed. The results show that at 40 Gb/s, a total channel loss up to 37 dB at the Nyquist frequency allows for error-free duobinary transmission, while a total channel loss of 42 dB was overcome with a BER below 10−8. An overview of the conclusions is summarized in Chapter 5, along with some suggestions for further research in this field. (1) The duobinary receiver was developed by my colleague Timothy De Keulenaer, as described in his PhD dissertation. (2) Described in the PhD dissertation of Timothy De Keulenaer

    Calliope, Volume 18, Number 2

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