Reliable and Efficient Parallel Processing Algorithms and Architectures for Modern Signal Processing

Least-squares (LS) estimations and spectral decomposition algorithms constitute the heart of modern signal processing and communication problems. Implementations of recursive LS and spectral decomposition algorithms onto parallel processing architectures such as systolic arrays with efficient fault-tolerant schemes are the major concerns of this dissertation. There are four major results in this dissertation. First, we propose the systolic block Householder transformation with application to the recursive least-squares minimization. It is successfully implemented on a systolic array with a two-level pipelined implementation at the vector level as well as at the word level. Second, a real-time algorithm-based concurrent error detection scheme based on the residual method is proposed for the QRD RLS systolic array. The fault diagnosis, order degraded reconfiguration, and performance analysis are also considered. Third, the dynamic range, stability, error detection capability under finite-precision implementation, order degraded performance, and residual estimation under faulty situations for the QRD RLS systolic array are studied in details. Finally, we propose the use of multi-phase systolic algorithms for spectral decomposition based on the QR algorithm. Two systolic architectures, one based on triangular array and another based on rectangular array, are presented for the multiphase operations with fault-tolerant considerations. Eigenvectors and singular vectors can be easily obtained by using the multi-pase operations. Performance issues are also considered

On recursive least-squares filtering algorithms and implementations

In many real-time signal processing applications, fast and numerically stable algorithms for solving least-squares problems are necessary and important. In particular, under non-stationary conditions, these algorithms must be able to adapt themselves to reflect the changes in the system and take appropriate adjustments to achieve optimum performances. Among existing algorithms, the QR-decomposition (QRD)-based recursive least-squares (RLS) methods have been shown to be useful and effective for adaptive signal processing. In order to increase the speed of processing and achieve high throughput rate, many algorithms are being vectorized and/or pipelined to facilitate high degrees of parallelism. A time-recursive formulation of RLS filtering employing block QRD will be considered first. Several methods, including a new non-continuous windowing scheme based on selectively rejecting contaminated data, were investigated for adaptive processing. Based on systolic triarrays, many other forms of systolic arrays are shown to be capable of implementing different algorithms. Various updating and downdating systolic algorithms and architectures for RLS filtering are examined and compared in details, which include Householder reflector, Gram-Schmidt procedure, and Givens rotation. A unified approach encompassing existing square-root-free algorithms is also proposed. For the sinusoidal spectrum estimation problem, a judicious method of separating the noise from the signal is of great interest. Various truncated QR methods are proposed for this purpose and compared to the truncated SVD method. Computer simulations provided for detailed comparisons show the effectiveness of these methods. This thesis deals with fundamental issues of numerical stability, computational efficiency, adaptivity, and VLSI implementation for the RLS filtering problems. In all, various new and modified algorithms and architectures are proposed and analyzed; the significance of any of the new method depends crucially on specific application

FPGA-based Low Latency Inverse QRD Architecture for Adaptive Beamforming in Phased Array Radars

The main objective of this paper is to facilitate the adaptive beamforming which is one of the most challenging task in phased array radars receivers. Recursive least square (RLS) is considered as the most well suited adaptive algorithm for the applications where beamforming is mandatory, because of its good numerical properties and convergence rate. In this paper, some RLS variants are discussed and the most numerically suitable algorithm Inverse QRD is selected for efficient adaptive beamforming. A novel architecture for IQRD RLS is also presented, which offers low latency and low area occupation for Field Programmable Gate Array (FPGA) implementation. This approach reduces the computations by utilizing the standard pipelining methodology. Hence, efficient adder and multipliers and LUT based solution for square root and division, has highly enhanced the performance of the algorithm. The proposed IQRD RLS architecture has been coded in Verilog and analyze its performance in terms of throughput, hardware resources and efficiency

Enabling VLSI processing blocks for MIMO-OFDM Communications

Multi-input multi-output (MIMO) systems combined with orthogonal frequency-division multiplexing (OFDM) gained a wide popularity in wireless applications due to the potential of providing increased channel capacity and robustness against multipath fading channels. However these advantages come at the cost of a very high processing complexity and the efficient implementation of MIMO-OFDM receivers is today a major research topic. In this paper, efficient architectures are proposed for the hardware implementation of the main building blocks of a MIMO-OFDM receiver. A sphere decoder architecture flexible to different modulation without any loss in BER performance is presented while the proposed matrix factorization implementation allows to achieve the highest throughput specified in the IEEE 802.11n standard. Finally a novel sphere decoder approach is presented, which allows for the realization of new golden space time trellis coded modulation (GST-TCM) scheme. Implementation cost and offered throughput are provided for the proposed architectures synthesized on a 0.13  CMOS standard cell technology or on advanced FPGA devices

Energy Efficient VLSI Circuits for MIMO-WLAN

Mobile communication - anytime, anywhere access to data and communication services - has been continuously increasing since the operation of the first wireless communication link by Guglielmo Marconi. The demand for higher data rates, despite the limited bandwidth, led to the development of multiple-input multiple-output (MIMO) communication which is often combined with orthogonal frequency division multiplexing (OFDM). Together, these two techniques achieve a high bandwidth efficiency. Unfortunately, techniques such as MIMO-OFDM significantly increase the signal processing complexity of transceivers. While fast improvements in the integrated circuit (IC) technology enabled to implement more signal processing complexity per chip, large efforts had and have to be done for novel algorithms as well as for efficient very large scaled integration (VLSI) architectures in order to meet today's and tomorrow's requirements for mobile wireless communication systems. In this thesis, we will present architectures and VLSI implementations of complete physical (PHY) layer application specific integrated circuits (ASICs) under the constraints imposed by an industrial wireless communication standard. Contrary to many other publications, we do not elaborate individual components of a MIMO-OFDM communication system stand-alone, but in the context of the complete PHY layer ASIC. We will investigate the performance of several MIMO detectors and the corresponding preprocessing circuits, being integrated into the entire PHY layer ASIC, in terms of achievable error-rate, power consumption, and area requirement. Finally, we will assemble the results from the proposed PHY layer implementations in order to enhance the energy efficiency of a transceiver. To this end, we propose a cross-layer optimization of PHY layer and medium access control (MAC) layer

Adaptive multiple symbol decision feedback for non-coherent detection.

Thesis (M.Sc.Eng.)-University of KwaZulu-Natal, Durban, 2006.Non-coherent detection is a simple form of signal detection and demodulation for digital communications. The main drawback of this detection method is the performance penalty incurred, since the channel state information is not known at the receiver. Multiple symbol detection (MSD) is a technique employed to close the gap between coherent and non-coherent detection schemes. Differentially encoded JW-ary phase shift keying (DM-PSK) is the classic modulation technique that is favourable for non-coherent detection. The main drawback for standard differential detection (SDD) has been the error floor incurred for frequency flat fading channels. Recently a decision feedback differential detection (DFDD) scheme, which uses the concept of MSD was proposed and offered significant performance gain over the SDD in the mobile flat fading channel, almost eliminating the error floor. This dissertation investigates multiple symbol decision feedback detection schemes, and proposes alternate adaptive strategies for non-coherent detection. An adaptive algorithm utilizing the numerically stable QR decomposition that does not require training symbols is proposed, named QR-DFDD. The QR-DFDD is modified to use a simpler QR decomposition method which incorporates sliding windows: QRSW-DFDD. This structure offers good tracking performance in flat fading conditions, while achieving near optimal DFDD performance. A bit interleaved coded decision feedback differential demodulation (DFDM) scheme, which takes advantage of the decision feedback concept and iterative decoding, was introduced by Lampe in 2001. This low complexity iterative demodulator relied on accurate channel statistics for optimal performance. In this dissertation an alternate adaptive DFDM is introduced using the recursive least squares (RLS) algorithm. The alternate iterative decoding procedure makes use of the convergence properties of the RLS algorithm that is more stable and achieves superior performance compared to the DFDM

Distributed Estimation in Wireless Sensor Networks: Robust Nonparametric and Energy Efficient Environment Monitoring

Wireless sensor networks estimate some parameters of interest associated with the environment by processing the spatio-temporal data. In classical methods the data collected at different sensor nodes are combined at the fusion center(FC) through multihop communications and the desired parameter is estimated. However, this requires a large number of communications which leads to a fast decay of energy at the sensor nodes. Different distributed strategies have been reported in literature which use the computational capability of the sensor nodes and the estimated local parameters of the neighborhood nodes to achieve the global parameters of interest. However all these distributed strategies are based on the least square error cost function which is sensitive to the outliers such as impulse noise and interference present in the desired and/or input data. Therefore there is need of finding the proper robust cost functions which would be suitable for wireless sensor network in terms of communication and computational complexities. This dissertation deals with the development of a number of robust distributed algorithms based on the notion of rank based nonparametric robust cost functions to handle outliers in the (i) desired data; (ii) input data; (iii) in both input and desired data; and (iv) desired data in case of highly colored input data. Exhaustive simulation studies show that the proposed methods are robust against 50% outliers in the data, provide better convergence and low mean square deviation. Further this thesis deals with a real world application of energy efficient environment monitoring. A minimum volume ellipsoid is formed using distributed strategy covering those sensor nodes which indicate the event of interest. In addition a novel technique is proposed for finding the incremental path for regularly placed sensor nodes. It is shown mathematically that the proposed distributed strategy enhances the lifetime of the entire network drastically

Design of software radio

Software Define Radio (SDR) has become a prevalent technology in wireless systems. In SDR some or all of the signal specific handling is implemented in software functions, while other functions like decimation, interpolation, digital up-conversion and digital down conversion are done on reprogrammable Digital Signal Processor or Field Programmable Gate Arrays.Twelve laboratory exercises have been designed to lead the student through the process of using the Universal Software Radio peripheral (USRP) hardware and GNU Radio open source software