221 research outputs found

    A novel approach to fast discrete Hartley transform

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    The Discrete Hartley transform (DHT) is an important tool in digital signal processing. We propose a novel approach to perform DHT. We transform DHT into a form expressed in discrete moments via a modular mapping and truncating Taylor series expansion and present a completely new formula for computing DHT. We extend the use of our systolic array for fast computation of moments without any multiplications, to one that computes DHT with only a few multiplications and without any evaluations of triangular functions. The multiplication number used in our method is O(Nlog2N/log2log2N) superior to O(Nlog 2N) in the conventional FDT. The execution time of the systolic array is only O(Nlog2N/log2log2N) for 1-D DHT and O(N k) for k-D DHT (kā©¾2). The systolic array consists of very simple processing elements and hence it implies an easy and potential hardware/VLSI implementation. The approach is also applicable to DHT inverses.published_or_final_versio

    Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier

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    Highly efficient arithmetic operations are necessary to achieve the desired performance in many real-time systems and digital image processing applications. In all these applications, one of the important arithmetic operations frequently performed is to multiply and accumulate with small computational time. In this paper, a 4-bit serial - parallel multiplier, which can perform both positive and negative multiplications, is presented. Baugh-Wooley algorithm necessitates complementation of last bit of each partial product except the last partial product in which all but the last bit are complemented. In the proposed algorithm all bits of the last partial product are complemented. This modification results in considerable reduction in hardware compared to Baugh-Wooley multiplier. This multiplier can be used for implementation of discrete orthogonal transforms, which are used in many applications, including image and signal processing. This paper presents a 2D bit-level systolic architecture for a matrixmatrix multiplier. A comparison with similar structures has shown that the proposed structure performs better

    DFT algorithms for bit-serial GaAs array processor architectures

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    Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology

    FPGA Implementation of DHT Algorithms for Image Compression

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    Digital image processing is the use of computer algorithms to perform image processing on digital images. The basic operation performed by a simple digital camera is, to convert the light energy to electrical energy, then the energy is converted to digital format and a compression algorithm is used to reduce memory requirement for storing the image. This compression algorithm is frequently called for capturing and storing the images. This leads us to develop an efficient compression algorithm which will give the same result as that of the existing algorithms with low power consumption. Compression is useful as it helps in reduction of the usage of expensive resources, such as memory (hard disks), or the transmission bandwidth required. But on the downside, compression techniques result in distortion (due to lossy compression schemes) and also additional computational resources are required for compression-decompression of the data. Reduction of these resources by comparing different algorithms for DHT is required. FPGA Implementations of different algorithms for 1-DHT using VHDL as the synthesis tool are carried out and their comparison gives the optimum technique for compression. Finally 2-D DHT is implemented using the optimum 1-D technique for 8x8 matrix input. The results obtained are discussed and improvements are suggested to further optimize the design

    Cardiovascular instrumentation for spaceflight

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    The observation mechanisms dealing with pressure, flow, morphology, temperature, etc. are discussed. The approach taken in the performance of this study was to (1) review ground and space-flight data on cardiovascular function, including earlier related ground-based and space-flight animal studies, Mercury, Gemini, Apollo, Skylab, and recent bed-rest studies, (2) review cardiovascular measurement parameters required to assess individual performance and physiological alternations during space flight, (3) perform an instrumentation survey including a literature search as well as personal contact with the applicable investigators, (4) assess instrumentation applicability with respect to the established criteria, and (5) recommend future research and development activity. It is concluded that, for the most part, the required instrumentation technology is available but that mission-peculiar criteria will require modifications to adapt the applicable instrumentation to a space-flight configuration
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