On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch

This paper describes the jitter problem in\ud DLL-based clock multipliers that arises due to stochastic\ud mismatch in the delay cells that are used in the Voltage Controlled\ud Delay Line of the DLL [1]. An analysis is presented\ud that relates the stochastic spread of the delay of the cells to\ud the output jitter of the clock multiplier. This analysis shows\ud that relative time deviations are highest in the middle of the\ud Delay Line and proportional to the square root of the frequency\ud multiplication factor of the structure. A circuit design\ud technique, called Impedance Level Scaling, is presented\ud that allows the designer to optimize the noise and mismatch\ud behavior of a circuit independent of other specifications such\ud as speed and linearity. Applying this technique on delay cell\ud design yields a direct trade-off between noise induced jitter\ud and power usage, and between stochastic mismatch induced\ud jitter and power usage

Geometrically-constrained, parasitic-aware synthesis of analog ICs

In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very time-consuming task: if circuit performance including layout-induced degradations proves unacceptable, a re-design cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenario is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layout-aware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how.Ministerio de Educación y Ciencia TEC2004-0175

Via-configurable transistors array: a regular design technique to improve ICs yield

Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Our objective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for Carry-Ripple Adders from 4 bits to 64 bits.Peer ReviewedPostprint (published version

PAD: A New Interactive Knowledge-Based Analog Design Approach

This paper presents a new Procedural Analog Design tool called PAD. It is a chart-based design environment dedicated to the design of analog circuits aiming to optimize design and quality by finding good tradeoffs. This interactive tool allows step-by-step design of analog cells by using guidelines for each analog topology. Its interactive interface enables instantaneous visualization of design tradeoffs. At each step, the user modifies interactively one subset of design parameters and observes the effect on other circuit parameters. At the end, an optimized design is ready for simulation (verification and fine-tuning). The present version of PAD covers the design of basic analog structures (one transistor or groups of transistors) and the procedural design of transconductance amplifiers (OTAs) and different operational amplifier topologies. The basic analog structures' calculator embedded in PAD uses the complete set of equations of the EKV MOS model, which links the equations for weak and strong inversion in a continuous way [1, 2]. Furthermore, PAD provides a layout generator for matched substructures such as current mirrors, cascode stages and differential pair

Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

Finite Element Method Modeling Of Advanced Electronic Devices

In this dissertation, we use finite element method together with other numerical techniques to study advanced electron devices. We study the radiation properties in electron waveguide structure with multi-step discontinuities and soft wall lateral confinement. Radiation mechanism and conditions are examined by numerical simulation of dispersion relations and transport properties. The study of geometry variations shows its significant impact on the radiation intensity and direction. In particular, the periodic corrugation structure exhibits strong directional radiation. This interesting feature may be useful to design a nano-scale transmitter, a communication device for future nano-scale system. Non-quasi-static effects in AC characteristics of carbon nanotube field-effect transistors are examined by solving a full time-dependent, open-boundary Schrödinger equation. The non-quasi-static characteristics, such as the finite channel charging time, and the dependence of small signal transconductance and gate capacitance on the frequency, are explored. The validity of the widely used quasi-static approximation is examined. The results show that the quasi-static approximation overestimates the transconductance and gate capacitance at high frequencies, but gives a more accurate value for the intrinsic cut-off frequency over a wide range of bias conditions. The influence of metal interconnect resistance on the performance of vertical and lateral power MOSFETs is studied. Vertical MOSFETs in a D2PAK and DirectFET package, and lateral MOSFETs in power IC and flip chip are investigated as the case studies. The impact of various layout patterns and material properties on RDS(on) will provide useful guidelines for practical vertical and lateral power MOSFETs design

A Reuse-based framework for the design of analog and mixed-signal ICs

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore's Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools and design methodologies -and, possibly, a design paradigm shift-that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design has hindered a similar level of consensus and development. This paper presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the two first for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. A case study and a functional silicon prototype demonstrate the validity of the paper's proposals.Ministerio de Educación y Ciencia TEC2004-0175

Current mode monolithic active pixel sensor with correlated double sampling for charged particle detection

A monolithic active pixel sensor operating in current mode for charged particle detection is described. The sensing element in each pixel is an n-well/p-sub diode with a PMOS transistor integrated in an n-well. The drop of the n-well potential from the collection of charge modulates the transistor channel current. Each pixel features two current mode memory cells. The subtraction of distant-in-time samples frees the signal of fixed pattern noise (FPN) and of the correlated low-frequency temporal noise components, resulting in extraction of the particle footprint. The subtraction circuits are placed at each column end. A transimpedance amplifier, integrating in sequence two current samples and subtracting the results in an arithmetic operation, was adopted. The integrated version of the transimpedance amplifier, designed with a maximized conversion gain, is burdened by a risk of an early saturation, imperiling its operation, if the dispersions of the dc current component are too big. The degree of dispersions could not be estimated during the design. Some number of columns is available as a backup with the direct current readout. An external realization of the subtracting circuit, based on the same principle, is used to process direct output columns. The concept of the data acquisition setup developed, the tested performance of an array of cells, and the processing circuitry are described