54 research outputs found

    SystemC-AMS Requirements, Design Objectives and Rationale

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    This paper presents and discusses the foundations on which the analog and mixed-signal extensions of SystemC, named SystemC-AMS, will be developed. First, requirements from targeted application domains are identified. These are then used to derive design objectives and related rationales. Finally, some preliminary seed work is presented and the outline of the analog and mixed-signal extensions development work is given

    On mixed abstraction, languages and simulation approach to refinement with SystemC AMS

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    Executable specifications and simulations arecornerstone to system design flows. Complex mixed signalembedded systems can be specified with SystemC AMSwhich supports abstraction and extensible models of computation. The language contains semantics for moduleconnections and synchronization required in analog anddigital interaction. Through the synchronization layer, user defined models of computation, solvers and simulators can be unified in the SystemC AMS simulator for achieving low level abstraction and model refinement. These improvements assist in amplifying model aspects and their contribution to the overall system behavior. This work presents cosimulating refined models with timed data flow paradigm of SystemC AMS. The methodology uses Cbased interaction between simulators. An RTL model ofdata encryption standard is demonstrated as an example.The methodology is flexible and can be applied in earlydesign decision trade off, architecture experimentation and particularly for model refinement and critical behavior analysis

    Re-use of tests and arguments for assesing dependable mixed-critically systems

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    The safety assessment of mixed-criticality systems (MCS) is a challenging activity due to system heterogeneity, design constraints and increasing complexity. The foundation for MCSs is the integrated architecture paradigm, where a compact hardware comprises multiple execution platforms and communication interfaces to implement concurrent functions with different safety requirements. Besides a computing platform providing adequate isolation and fault tolerance mechanism, the development of an MCS application shall also comply with the guidelines defined by the safety standards. A way to lower the overall MCS certification cost is to adopt a platform-based design (PBD) development approach. PBD is a model-based development (MBD) approach, where separate models of logic, hardware and deployment support the analysis of the resulting system properties and behaviour. The PBD development of MCSs benefits from a composition of modular safety properties (e.g. modular safety cases), which support the derivation of mixed-criticality product lines. The validation and verification (V&V) activities claim a substantial effort during the development of programmable electronics for safety-critical applications. As for the MCS dependability assessment, the purpose of the V&V is to provide evidences supporting the safety claims. The model-based development of MCSs adds more V&V tasks, because additional analysis (e.g., simulations) need to be carried out during the design phase. During the MCS integration phase, typically hardware-in-the-loop (HiL) plant simulators support the V&V campaigns, where test automation and fault-injection are the key to test repeatability and thorough exercise of the safety mechanisms. This dissertation proposes several V&V artefacts re-use strategies to perform an early verification at system level for a distributed MCS, artefacts that later would be reused up to the final stages in the development process: a test code re-use to verify the fault-tolerance mechanisms on a functional model of the system combined with a non-intrusive software fault-injection, a model to X-in-the-loop (XiL) and code-to-XiL re-use to provide models of the plant and distributed embedded nodes suited to the HiL simulator, and finally, an argumentation framework to support the automated composition and staged completion of modular safety-cases for dependability assessment, in the context of the platform-based development of mixed-criticality systems relying on the DREAMS harmonized platform.La dificultad para evaluar la seguridad de los sistemas de criticidad mixta (SCM) aumenta con la heterogeneidad del sistema, las restricciones de diseño y una complejidad creciente. Los SCM adoptan el paradigma de arquitectura integrada, donde un hardware embebido compacto comprende múltiples plataformas de ejecución e interfaces de comunicación para implementar funciones concurrentes y con diferentes requisitos de seguridad. Además de una plataforma de computación que provea un aislamiento y mecanismos de tolerancia a fallos adecuados, el desarrollo de una aplicación SCM además debe cumplir con las directrices definidas por las normas de seguridad. Una forma de reducir el coste global de la certificación de un SCM es adoptar un enfoque de desarrollo basado en plataforma (DBP). DBP es un enfoque de desarrollo basado en modelos (DBM), en el que modelos separados de lógica, hardware y despliegue soportan el análisis de las propiedades y el comportamiento emergente del sistema diseñado. El desarrollo DBP de SCMs se beneficia de una composición modular de propiedades de seguridad (por ejemplo, casos de seguridad modulares), que facilitan la definición de líneas de productos de criticidad mixta. Las actividades de verificación y validación (V&V) representan un esfuerzo sustancial durante el desarrollo de aplicaciones basadas en electrónica confiable. En la evaluación de la seguridad de un SCM el propósito de las actividades de V&V es obtener las evidencias que apoyen las aseveraciones de seguridad. El desarrollo basado en modelos de un SCM incrementa las tareas de V&V, porque permite realizar análisis adicionales (por ejemplo, simulaciones) durante la fase de diseño. En las campañas de pruebas de integración de un SCM habitualmente se emplean simuladores de planta hardware-in-the-loop (HiL), en donde la automatización de pruebas y la inyección de faltas son la clave para la repetitividad de las pruebas y para ejercitar completamente los mecanismos de tolerancia a fallos. Esta tesis propone diversas estrategias de reutilización de artefactos de V&V para la verificación temprana de un MCS distribuido, artefactos que se emplearán en ulteriores fases del desarrollo: la reutilización de código de prueba para verificar los mecanismos de tolerancia a fallos sobre un modelo funcional del sistema combinado con una inyección de fallos de software no intrusiva, la reutilización de modelo a X-in-the-loop (XiL) y código a XiL para obtener modelos de planta y nodos distribuidos aptos para el simulador HiL y, finalmente, un marco de argumentación para la composición automatizada y la compleción escalonada de casos de seguridad modulares, en el contexto del desarrollo basado en plataformas de sistemas de criticidad mixta empleando la plataforma armonizada DREAMS.Kritikotasun nahastuko sistemen segurtasun ebaluazioa jarduera neketsua da beraien heterogeneotasuna dela eta. Sistema hauen oinarria arkitektura integratuen paradigman datza, non hardware konpaktu batek exekuzio plataforma eta komunikazio interfaze ugari integratu ahal dituen segurtasun baldintza desberdineko funtzio konkurrenteak inplementatzeko. Konputazio plataformek isolamendu eta akatsen aurkako mekanismo egokiak emateaz gain, segurtasun arauek definituriko jarraibideak jarraitu behar dituzte kritikotasun mistodun aplikazioen garapenean. Sistema hauen zertifikazio prozesuaren kostua murrizteko aukera bat plataformetan oinarritutako garapenean (PBD) datza. Garapen planteamendu hau modeloetan oinarrituriko garapena da (MBD) non modeloaren logika, hardware eta garapen desberdinak sistemaren propietateen eta portaeraren aurka aztertzen diren. Kritikotasun mistodun sistemen PBD garapenak etekina ateratzen dio moduluetan oinarrituriko segurtasun propietateei, adibidez: segurtasun kasu modularrak (MSC). Modulu hauek kritikotasun mistodun produktu-lerroak ere hartzen dituzte kontutan. Berifikazio eta balioztatze (V&V) jarduerek esfortzu kontsideragarria eskatzen dute segurtasun-kiritikoetarako elektronika programagarrien garapenean. Kritikotasun mistodun sistemen konfiantzaren ebaluazioaren eta V&V jardueren helburua segurtasun eskariak jasotzen dituzten frogak proportzionatzea da. Kritikotasun mistodun sistemen modelo bidezko garapenek zeregin gehigarriak atxikitzen dizkio V&V jarduerari, fase honetan analisi gehigarriak (hots, simulazioak) zehazten direlako. Bestalde, kritikotasun mistodun sistemen integrazio fasean, hardware-in-the-loop (Hil) simulazio plantek V&V iniziatibak sostengatzen dituzte non testen automatizazioan eta akatsen txertaketan funtsezko jarduerak diren. Jarduera hauek frogen errepikapena eta segurtasun mekanismoak egiaztzea ahalbidetzen dute. Tesi honek V&V artefaktuen berrerabilpenerako estrategiak proposatzen ditu, kritikotasun mistodun sistemen egiaztatze azkarrerako sistema mailan eta garapen prozesuko azken faseetaraino erabili daitezkeenak. Esate baterako, test kodearen berrabilpena akats aurkako mekanismoak egiaztatzeko, modelotik X-in-the-loop (XiL)-ra eta kodetik XiL-rako konbertsioa HiL simulaziorako eta argumentazio egitura bat DREAMS Europear proiektuan definituriko arkitektura estiloan oinarrituriko segurtasun kasu modularrak automatikoki eta gradualki sortzeko

    Modeling Heterogeneous SoCs with SystemC: A Digital/MEMS Case Study

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    Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital parts of a system. This is a significant limitation, making it difficult to perform key system design tasks — design space exploration, hardware-software co-design and system verification — at an early stage. This paper describes lumped analytical models of a class of complex non-digital devices — MEMS microhotplates — and presents techniques to integrate them into a SystemC simulation of a heterogeneous System-on-a-Chip (SoC). This approach makes the MEMS component behavior visible to a full-system simulation at higher levels, enabling realistic system design and testing. The contributions made in this work include the first SystemC models of a MEMS-based SoC, the first modeling of MEMS thermal behavior in SystemC, and a detailed case study of the application of these techniques to a real system. In addition, this work provides insights into how MEMS device-level design decisions can significantly impact system level behavior; it also describes how full-system modeling can help detect such phenomena and help to address detected problems early in the design flow

    Wireless extension to the existing SystemC design methodology

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    This research uses a SystemC design methodology to model and design complex wireless communication systems, because in the recent years, the complexity of wireless communication systems has increased and the modelling and design of such systems has become inefficient and challenging. The most important aspect of modelling wireless communication systems is that system design choices may affect the communication behaviour and also communication design choices may impact on the system design. Whilst, the SystemC modelling language shows great promise in the modelling of complex hardware/software systems, it still lacks a standard framework that supports modelling of wireless communication systems (particularly the use of wireless communication channels). SystemC lacks elements and components that can be used to express and simulate wireless systems. It does not support noise links natively. To fill this gap, this research proposes to extend the existing SystemC design methodology to include an efficient simulation of wireless systems. It proposes to achieve this by employing a system-level model of a noisy wireless communication channel, along with a small repertoire of standard components (which of course can be replaced on a per application basis). Finally, to validate our developed methodology, a flocking behaviour system is selected as a demonstration (case study). This is a very complex system modelled based on the developed methodology and partitioned along different parameters. By applying our developed methodology to model this system as a case study, we can prove that incorporating and fixing the wireless channel, wireless protocol, noise or all of these elements early in the design methodology is very advantageous. The modelled system is introduced to simulate the behaviour of the particles (mobile units) that form a mobile ad-hoc communication network. Wireless communication between particles is addressed with two scenarios: the first is created using a wireless channel model to link each pair of particles, which means the wireless communication between particles is addressed using a Point-to-Point (P2P) channel; the other scenario is created using a shared channel (broadcast link). Therefore, incorporating wireless features into existing SystemC design methodology, as done in this research, is a very important task, because by developing SystemC as a design tool to support wireless systems, hardware aspects, software parts and communication can be modelled, refined and validated simultaneously on the same platform, and the design space expanded into a two-dimensional design space comprising system and communication

    Efficient Modelling and Simulation Methodology for the Design of Heterogeneous Mixed-Signal Systems on Chip

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    Systems on Chip (SoCs) and Systems in Package (SiPs) are key parts of a continuously broadening range of products, from chip cards and mobile phones to cars. Besides an increasing amount of digital hardware and software for data processing and storage, they integrate more and more analogue/RF circuits, sensors, and actuators to interact with their (analogue) environment. This trend towards more complex and heterogeneous systems with more intertwined functionalities is made possible by the continuous advances in the manufacturing technologies and pushed by market demand for new products and product variants. Therefore, the reuse and retargeting of existing component designs becomes more and more important. However, all these factors make the design process increasingly complex and multidisciplinary. Nowadays, the design of the individual components is usually well understood and optimised through the usage of a diversity of CAD/EDA tools, design languages, and data formats. These are based on applying specific modelling/abstraction concepts, description formalisms (also called Models of Computation (MoCs)) and analysis/simulation methods. The designer has to bridge the gaps between tools and methodologies using manual conversion of models and proprietary tool couplings/integrations, which is error-prone and time-consuming. A common design methodology and platform to manage, exchange, and collaboratively develop models of different formats and of different levels of abstraction is missing. The verification of the overall system is a big problem, as it requires the availability of compatible models for each component at the right level of abstraction to achieve satisfying results with respect to the system functionality and test coverage, but at the same time acceptable simulation performance in terms of accuracy and speed. Thus, the big challenge is the parallel integration of these very different part design processes. Therefore, the designers need a common design and simulation platform to create and refine an executable specification of the overall system (a virtual prototype) on a high level of abstraction, which supports different MoCs. This makes possible the exploration of different architecture options, estimation of the performance, validation of re-used parts, verification of the interfaces between heterogeneous components and interoperability with other systems as well as the assessment of the impacts of the future working environment and the manufacturing technologies used to realise the system. For embedded Analogue and Mixed-Signal (AMS) systems, the C++-based SystemC with its AMS extensions, to which recent standardisation the author contributed, is currently establishing itself as such a platform. This thesis describes the author's contribution to solve the modelling and simulation challenges mentioned above in three thematic phases. In the first phase, the prototype of a web-based platform to collect models from different domains and levels of abstraction together with their associated structural and semantical meta information has been developed and is called ModelLib. This work included the implementation of a hierarchical access control mechanism, which is able to protect the Intellectual Property (IP) constituted by the model at different levels of detail. The use cases developed for this tool show how it can support the AMS SoC design process by fostering the reuse and collaborative development of models for tasks like architecture exploration, system validation, and creation of more and more elaborated models of the system. The experiences from the ModelLib development delivered insight into which aspects need to be especially addressed throughout the development of models to make them reusable: mainly flexibility, documentation, and validation. This was the starting point for the development of an efficient modelling methodology for the top-down design and bottom-up verification of RF Systems based on the systematic usage of behavioural models in the second phase. One outcome is the developed library of well documented, parameterisable, and pin-accurate VHDL-AMS models of typical analogue/digital/RF components of a transceiver. The models offer the designer two sets of parameters: one based on the performance specifications and one based on the device parameters back-annotated from the transistor-level implementation. The abstraction level used for the description of the respective analogue/digital/RF component behaviour has been chosen to achieve a good trade-off between accuracy, fidelity, and simulation performance. The pin-accurate model interfaces facilitate the integration of transistor-level models for the validation of the behavioural models or the verification of a component implementation in the system context. These properties make the models suitable for different design tasks such as architecture exploration or overall system validation. This is demonstrated on a model of a binary Frequency-Shift Keying (FSK) transmitter parameterised to meet very different target specifications. This project showed also the limits in terms of abstraction and simulation performance of the "classical" AMS Hardware Description Languages (HDLs). Therefore, the third and last phase was dedicated to further raise the abstraction level for the description of complex and heterogeneous AMS SoCs and thus enable their efficient simulation using different synchronised MoCs. This work uses the C++-based simulation framework SystemC with its AMS extensions. New modelling capabilities going beyond the standardised SystemC AMS extensions have been introduced to describe energy conserving multi-domain systems in a formal and consistent way at a high level of abstraction. To this end, all constants, variables, and parameters of the system model, which represent a physical quantity, can now declare their dimension and associated system of units as an intrinsic part of their data type. Assignments to them need to contain besides the value also the correct measurement unit. This allows a much more precise but still compact definition of the models' interfaces and equations. Thus, the C++ compiler can check the correct assembly of the components and the coherency of the equations by means of dimensional analysis. The implementation is based on the Boost.Units library, which employs template metaprogramming techniques. A dedicated filter for the measurement units data types has been implemented to simplify the compiler messages and thus facilitate the localisation of unit errors. To ensure the reusability of models despite precisely defined interfaces, their interfaces and behaviours need to be parametrisable in a well-defined manner. The enabling implementation techniques for this have been demonstrated with the developed library of generic block diagram component models for the Timed Data Flow (TDF) MoC of the SystemC AMS extensions. These techniques are also the key to integrate a new MoC based on the bond graph formalism into the SystemC AMS extensions. Bond graphs facilitate the unified description of the energy conserving parts of heterogeneous systems with the help of a small set of modelling primitives parametrisable to the physical domain. The resulting models have a simulation performance comparable to an equivalent signal flow model

    Continuous/Discrete Co-Simulation Interfaces from Formalization to Implementation

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    ABSTRACT Today’s systems-on-chip are growing in complexity as a result of a higher density of components on the same chip, and also on account of the heterogeneity of different modules that are particular to different application domains (i.e. mechanical, electrical, optical, biological and chemical). These systems can be found in a broad and diverse spectrum of applications in many industries, including but not limited to Automotive, Aerospace, Health Care and, Consumer Electronics. These multi-domain heterogeneous systems enable new applications and the creation of new markets. This thesis focuses on the design and the simulation of heterogeneous embedded systems, more specifically on continuous/discrete heterogeneous systems. Continuous-time and discrete-event models are at the core of the design of multi-domain systems. We present here a generic, language independent methodology for the design of continuous/discrete heterogeneous systems. This methodology is the basis for design of a new framework providing the interfaces that are in charge with the heterogeneous components adaptation. The methodology was successfully used for the implementation of different continuous/discrete systems such as: a glycemia level regulator, an analog/digital converter, a PID controller, a production chain control system and wimax system. Parts of the proposed methodology were adapted for the formalization, modeling and verification of an optical network on chip.---------- RÉSUMÉ Les systèmes sur puce sont de plus en plus complexes, pas seulement en terme de densité de composants sur la même puce mais aussi en terme d‘hétérogénéité des modules spécifiques pour différents domaines d’application (mécanique, électrique, optique, biologique chimique). On retrouve ces systèmes dans un grand éventail d’applications et dans divers industries tels que l’automobile, l’aéronautique, la santé, l’électroniques et autres. Ces systèmes hétérogènes multi-domaine permettent de nouvelles applications et la création de nouveaux marchés. Cette thèse se concentre sur la conception et la simulation des systèmes hétérogènes embarqués. Les modèles temps-continu et événement discret sont le noyau de la conception des systèmes multi-domaine. On présente ici l’analyse de modèles d’exécution et modèles de synchronisation des systèmes hétérogènes continu/discret, la définition d’une méthodologie générique pour la conception des outils de co-simulation des systèmes hétérogènes continus/discrets et la validation de la méthodologie par applications – la réalisation d’un cadre de co-simulation pour les systèmes continu/discret. La méthodologie exploite les techniques de vérification formelle et de la simulation. La conception des outils de simulation est basée sur la définition d’une architecture générique des interfaces de simulation ainsi que sur des modèles de synchronisation vérifiés formellement. La méthodologie a été utilisée pour l’implémentation d’un régulateur de niveau de glycémie. Une partie de la méthodologie a été adaptée pour la formalisation, la modélisation et la vérification formelle d’un réseau optique sur puce

    Génération de modèles de haut niveau enrichis pour les systèmes hétérogènes et multiphysiques

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    Systems on chip are more and more complex as they now embed not only digital and analog parts, butalso sensors and actuators. SystemC and its extension SystemC AMS allow the high level modeling ofsuch systems. These tools are efficient for feasibility study, architectural exploration and globalverification of heterogeneous and multiphysics systems. At low level of abstraction, the simulationdurations are too important. Moreover, synchronization problems appear when cosimulations areperformed. It is possible to abstract the low level models that are developed by the specialists of thedifferent domains to create high level models that can be simulated faster using SystemC/SystemCAMS. The models of computation and the modeling styles have been studied. A relation is shownbetween the modeling style, the model size and the simulation speed. A method that generatesautomatically the high level model of an analog linear circuit from its low level representation isproposed. Then, it is shown how to include in the high level model some information allowing thepower consumption estimation. After that, the multiphysics systems modeling is studied. Twomethods are discussed: firstly, the one that uses the electrical equivalent circuit, then the one based onthe bond graph approach. It is shown how to generate a bond graph equivalent model from a low levelrepresentation. Finally, the modeling of a wind turbine system is discussed in order to illustrate thedifferent concepts presented in this thesis.Les systèmes sur puce sont de plus en plus complexes : ils intègrent des parties numériques, desparties analogiques et des capteurs ou actionneurs. SystemC et son extension SystemC AMSpermettent aujourd’hui de modéliser à haut niveau d’abstraction de tels systèmes. Ces outilsconstituent de véritables atouts dans une optique d’étude de faisabilité, d’exploration architecturale etde vérification du fonctionnement global des systèmes complexes hétérogènes et multiphysiques. Eneffet, les durées de simulation deviennent trop importantes pour envisager les simulations globales àbas niveau d’abstraction. De plus, les simulations basées sur l’utilisation conjointe de différents outilsprovoquent des problèmes de synchronisation. Les modèles de bas niveau, une fois crées par lesspécialistes des différents domaines peuvent toutefois être abstraits afin de générer des modèles dehaut niveau simulables sous SystemC/SystemC AMS en des temps de simulation réduits. Une analysedes modèles de calcul et des styles de modélisation possibles est d’abord présentée afin d’établir unlien avec les durées de simulation, ceci pour proposer un style de modélisation en fonction du niveaud’abstraction souhaité et de l’ampleur de la simulation à effectuer. Dans le cas des circuits analogiqueslinéaires, une méthode permettant de générer automatiquement des modèles de haut niveaud’abstraction à partir de modèles de bas niveau a été proposée. Afin d’évaluer très tôt dans le flot deconception la consommation d’un système, un moyen d’enrichir les modèles de haut niveaupréalablement générés est présenté. L’attention a ensuite été portée sur la modélisation à haut niveaudes systèmes multiphysiques. Deux méthodes y sont discutées : la méthode consistant à utiliser lecircuit équivalent électrique puis la méthode basée sur les bond graphs. En particulier, nous proposonsune méthode permettant de générer un modèle équivalent au bond graph à partir d’un modèle de basniveau. Enfin, la modélisation d’un système éolien est étudiée afin d’illustrer les différents conceptsprésentés dans cette thèse

    Méthode de modélisation et de raffinement pour les systèmes hétérogènes. Illustration avec le langage System C-AMS

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    Les systèmes sur puces intègrent aujourd hui sur le même substrat des parties analogiques et des unités de traitement numérique. Tandis que la complexité de ces systèmes s accroissait, leur temps de mise sur le marché se réduisait. Une conception descendante globale et coordonnée du système est devenue indispensable de façon à tenir compte des interactions entre les parties analogiques et les partis numériques dès le début du développement. Dans le but de répondre à ce besoin, cette thèse expose un processus de raffinement progressif et méthodique des parties analogiques, comparable à ce qui existe pour le raffinement des parties numériques. L'attention a été plus particulièrement portée sur la définition des niveaux analogiques les plus abstraits et à la mise en correspondance des niveaux d abstraction entre parties analogiques et numériques. La cohérence du raffinement analogique exige de détecter le niveau d abstraction à partir duquel l utilisation d un modèle trop idéalisé conduit à des comportements irréalistes et par conséquent d identifier l étape du raffinement à partir de laquelle les limitations et les non linéarités aux conséquences les plus fortes sur le comportement doivent être introduites. Cette étape peut être d un niveau d'abstraction élevé. Le choix du style de modélisation le mieux adapté à chaque niveau d'abstraction est crucial pour atteindre le meilleur compromis entre vitesse de simulation et précision. Les styles de modélisations possibles à chaque niveau ont été examinés de façon à évaluer leur impact sur la simulation. Les différents modèles de calcul de SystemC-AMS ont été catégorisés dans cet objectif. Les temps de simulation obtenus avec SystemC-AMS ont été comparés avec Matlab Simulink. L'interface entre les modèles issus de l'exploration d'architecture, encore assez abstraits, et les modèles plus fin requis pour l'implémentation, est une question qui reste entière. Une bibliothèque de composants électroniques complexes décrits en SystemC-AMS avec le modèle de calcul le plus précis (modélisation ELN) pourrait être une voie pour réussir une telle interface. Afin d illustrer ce que pourrait être un élément d une telle bibliothèque et ainsi démontrer la faisabilité du concept, un modèle d'amplificateur opérationnel a été élaboré de façon à être suffisamment détaillé pour prendre en compte la saturation de la tension de sortie et la vitesse de balayage finie, tout en gardant un niveau d'abstraction suffisamment élevé pour rester indépendant de toute hypothèse sur la structure interne de l'amplificateur ou la technologie à employer.Systems on Chip (SoC) embed in the same chip analogue parts and digital processing units. While their complexity is ever increasing, their time to market is becoming shorter. A global and coordinated top-down design approach of the whole system is becoming crucial in order to take into account the interactions between the analogue and digital parts since the beginning of the development. This thesis presents a systematic and gradual refinement process for the analogue parts comparable to what exists for the digital parts. A special attention has been paid to the definition of the highest abstracted analogue levels and to the correspondence between the analogue and the digital abstraction levels. The analogue refinement consistency requires to detect the abstraction level where a too idealised model leads to unrealistic behaviours. Then the refinement step consist in introducing for instance the limitations and non-linearities that have a strong impact on the behaviour. Such a step can be done at a relatively high level of abstraction. Correctly choosing a modelling style, that suits well an abstraction level, is crucial to obtain the best trade-off between the simulation speed and the accuracy. The modelling styles at each abstraction level have been examined to understand their impact on the simulation. The SystemC-AMS models of computation have been classified for this purpose. The SystemC-AMS simulation times have been compared to that obtained with Matlab Simulink. The interface between models arisen from the architectural exploration still rather abstracted and the more detailed models that are required for the implementation, is still an open question. A library of complex electronic components described with the most accurate model of computation of SystemC-AMS (ELN modelling) could be a way to achieve such an interface. In order to show what should be an element of such a library, and thus prove the concept, a model of an operational amplifier has been elaborated. It is enough detailed to take into account the output voltage saturation and the finite slew rate of the amplifier. Nevertheless, it remains sufficiently abstracted to stay independent from any architectural or technological assumption.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF
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