169,531 research outputs found
A system-on-chip digital pH meter for use in a wireless diagnostic capsule
This paper describes the design and implementation of a system-on-chip digital pH meter, for use in a wireless capsule application. The system is organized around an 8-bit microcontroller, designed to be functionally identical to the Motorola 6805. The analog subsystem contains a floating-electrode ISFET, which is fully compatible with a commercial CMOS process. On-chip programmable voltage references and multiplexors permit flexibility with the minimum of external connections. The chip is designed in a modular fashion to facilitate verification and component re-use. The single-chip pH meter can be directly connected to a personal computer, and gives a response of 37 bits/pH, within an operating range of 7 pH units
Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS
The RD53 collaboration is currently designing a large scale prototype pixel
readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC.
The RD53A chip will be available by the end of the year 2017 and will be
extensively tested to confirm if the circuit and the architecture make a solid
foundation for the final pixel readout chips for the experiments at the HL-LHC.
A test and data acquisition system for the RD53A chip is currently under
development to perform single-chip and multi-chip module measurements. In
addition, the verification of the RD53A design is performed in a dedicated
simulation environment. The concept and the implementation of the test and data
acquisition system and the simulation environment, which are based on a modular
data acquisition and system testing framework, are presented in this work
A case study for NoC based homogeneous MPSoC architectures
The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this paper, a complete design methodology that tackles at once the aspects of system level modeling, hardware architecture, and programming model has been successfully used for the implementation of a multiprocessor network-on-chip (NoC)-based system, the NoCRay graphic accelerator. The design, based on 16 processors, after prototyping with field-programmable gate array (FPGA), has been laid out in 90-nm technology. Post-layout results show very low power, area, as well as 500 MHz of clock frequency. Results show that an array of small and simple processors outperform a single high-end general purpose processo
Tactile sensing chips with POSFET array and integrated interface electronics
This work presents the advanced version of novel POSFET (Piezoelectric Oxide Semiconductor Field Effect Transistor) devices based tactile sensing chip. The new version of the tactile sensing chip presented here comprises of a 4 x 4 array of POSFET touch sensing devices and integrated interface electronics (i.e. multiplexers, high compliance current sinks and voltage output buffers). The chip also includes four temperature diodes for the measurement of contact temperature. Various components on the chip have been characterized systematically and the overall operation of the tactile sensing system has been evaluated. With new design the POSFET devices have improved performance (i.e. linear response in the dynamic contact forces range of 0.01–3N and sensitivity (without amplification) of 102.4 mV/N), which is more than twice the performance of their previous implementations. The integrated interface electronics result in reduced interconnections which otherwise would be needed to connect the POSFET array with off-chip interface electronic circuitry. This research paves the way for CMOS (Complementary Metal Oxide Semiconductor) implementation of full on-chip tactile sensing systems based on POSFETs
A VLSI single chip (255,223) Reed-Solomon encoder with interleaver
A single-chip implementation of a Reed-Solomon encoder with interleaving capability is described. The code used was adapted by the CCSDS (Consulative Committee on Space Data Systems). It forms the outer code of the NASA standard concatenated coding system which includes a convolutional inner code of rate 1/2 and constraint length 7. The architecture, leading to this single VLSI chip design, makes use of a bit-serial finite field multiplication algorithm due to E.R. Berlekamp
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Cross-Layer Pathfinding for Off-Chip Interconnects
Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects
Driving electronics for OLED lighting
This paper proposes the concept of integrating an OLED (foil) and its driving electronics into one module. A complete light system consisting of these modules is the ultimate goal of this work. The main focus in this article is on the design of the driver chip and the circuit implementation. The measurement results confirm that it is possible to control the light output of the different modules
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