168 research outputs found

    Development of a Multi-Standard Protocol Using Software Defined Radio for a Mobile Station Transceiver

    Get PDF
    In this thesis, the Software Defined Radio Digital Control System (SDR DCS) has been developed to perform a multi-standard protocol of the handset using the GSM and CDMA systems. The SDR DCS was designed for the SDR based band digital transceiver of the handset as a control and protocol software to control and handle the operation of the handset when roaming between different protocols; it could easily and quickly let the handset reconfigure with the future protocol; it configured the handset with either of the GSM or CDMA protocol software, and scheduled for reconfiguration of the handset with the second protocol in sequence. The SDR DCS controls the download of the specific air interface environment. In order to implement the whole design in software, the design had to go through three stages. The first stage was to do all the design steps in the software using generic computing resources such as Hardware Description Language (HDL), with the top-level design for each protocol. The second stage was to define a logic circuit to perform the signal processing for each protocol; this step was applied after the simulation and synthesis, and eventually programming that circuit into the FPGA board. The third stage was to use the FPGA to implement the functions required for each protocol which constitutes the multi-standard protocol. The VHDL files were created for each element of the GSM and CDMA protocols. The GSM related system was developed with encoders and decoders linked to the channel model. The CDMA related system was designed with a transmitter to encode the user’s data into wide bandwidth using a reverse link channel and a synchronized receiver to receive the signal from the forward link channel and decode the wide bandwidth to recover the base band user’s data. The Synopsys™ software package was used for the design, synthesis and simulation of the SDR base band platform. The simulation tools used include the Model Sim and System Studio. Meanwhile, the Xilinx ISE 9.2i was used as the synthesis tool. The results of the simulated and synthesized top-level design files were downloaded into the Xilinx XSA-3S1000 FPGA board. The waveforms for the GSM and CDMA outputs approximately matched the ones seen in the oscilloscope for the FPGA output pin. This proved that the SDR DCS had successfully implemented its task, according to the objectives of the design

    The effects of part commonality on product development lead time

    Get PDF
    Thesis (S.M.)--Massachusetts Institute of Technology, System Design & Management Program, 2005.Includes bibliographical references (p. 131-132).Nortel Networks, a leading global supplier of telecommunications equipment, is engaged in an increasingly competitive global market place. Within this market, Nortel Networks is positioning itself as the leader of global network transformation. The vision of the new transformed network is one in which disparate network elements are converged onto single architectural platforms serving the Client, Wireless Access, Network Services, Multi-services Packet, VoIP, Multi-services Optical and Element Management aspects of the newly transformed network architecture. This paper focuses specifically on the hardware development process associated with the CDMA wireless access element referred to as a base transceiver station (BTS) in the transformed network. The effect of part commonality on product development lead times are investigated at four levels of integration: common part (ASIC), common assembly (circuit pack), common field replaceable unit (module) and finally the common platform (BTS). At increasing levels of integration, the use of common parts leads to longer product development lead times. This observation is examined using two methodologies. The first methodology utilizes the three lenses framework focusing primarily on the impacts of organizational structure on the product development process. An evaluation of the existing barriers preventing joint gains and acceptable compromises to be achieved amongst share holders in joint development programs is discussed. Methods by which to minimize the impact of organizational structure on common product development lead time are given and comparisons are made with alternate organizational models from within the telecommunications industry. The second methodology employed utilizes task(cont.) design structure matrices (DSM) to analyze the implication of part commonality on product development lead times for projects structured in accordance with the Nortel Networks Life Cycle Management model. Effects modeled include stochastic durations, probabilistic iterations, learning effects, resource constraints, parallel tasks and overlapping tasks. An evaluation of the results indicates an increased sensitivity to extended product development lead times associated with probabilistic iterations. This is shown to be particularly evident during the requirements definition phase in which multiple stakeholder requirements must be captured comprehensively. This sensitivity is amplified by the fact that product verification takes place in multiple labs each exercising the equipment in unique and un-accounted for configurations. Based on the above analysis, a framework to ascertain the optimum level of commonality to pursue on a given product is given.by Nicholas Svensson.S.M

    Domain specific high performance reconfigurable architecture for a communication platform

    Get PDF

    Editorial

    Get PDF

    Implementation of a FFT/IFFT Module on FPGA: Comparison of Methodologies

    Get PDF
    In this work, we have compared three different methodologies for the implementation of a FFT/IFFT module on FPGA: VHDL coding (VC), System-level tools at RT level (STR), and System-level tools at macroblock level (STM). In terms of resource usage and operation frequency, STM has obtained interesting results, although it has an important restriction about internal data width which produces a mean output error of 2.1%. VC and STR become a more general alternative that yields to a lower mean error (1.0%). Thus, we propose to combine VC and STR in order to facilitate the design process as well as allow designers to maintain total control over the module internal architecture and obtain an efficient structure

    VHDL-AMS modeling and simulation of a direct sequence spread spectrum (DS-SS) transmitter

    Get PDF
    Many recent standards in telecommunications field are based on CDMA spread spectrum transmissions. In this paper, we describe a methodology for top-down design, modeling, and simulation of CDMA transmitter system using hardware description language VHDL-AMS. Details of VHDL-AMS implementation for each elementary block are shown. This paper together with the developed library of CDMA transmitter blocks are targeted towards engineers who work on behavioral modeling and simulation of complete CDMA systems using hardware description languages

    Wideband active envelope load-pull for robust power amplifier and transistor characterisation

    Get PDF
    The advent of fourth generation (4G) wireless communication with available modulation bandwidth ranging from 1 MHz to 20 MHz is starting to emerge. The linear modulation technique being employed means that the power amplifiers that support the standards need to have high degree of linearity. By nature, however, all power amplifiers are non-linear. Load-pull measurement system provides anindispensable non-linear tool for the characterization of power amplifier and transistor for linearity enhancement. Conventional passive or active load-pull has delay problem that get worse as the modulation frequency is increased beyond few MHz. Furthermore in order to provide robust non-linear measurement, load-pull system needs to provide bandwidth at least five times the modulation bandwidth by including the fifth-order inter-modulation (IMD5). This thesis presents, for the first time, delay compensation on the unique active envelope load-pull architecture providing constant impedance for bandwidth up to 20 MHz. In doing so, it provides a superior load-pull measurement and also the ability to directly control in-band impedances. Artificial variations imposed on the in-band impedances offer further insight on power amplifier and transistor behaviours under wideband multi-tone stimulus.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

    IP protection for DSP algorithms\u27 FPGA implementation.

    Get PDF
    With today\u27s system-on-chip (SOC) technology, we are able to design larger and more complicated application-specific integrated circuits (ASICs) and field programmable gate array (FPGA) in shorter time period. The key point of the success of SOC technology is the reuse of intellectual property (IP) cores. Consequently the copyright protection for these IP cores becomes the major concern for the development pace of SOC technology. Watermarking technology has been proved to be an effective way of copyright protection. In this thesis, the author presents two new watermarking algorithms respectively at algorithm level and FPGA layout level. The simulations and implementation results show that the new proposals have much less design and hardware implementation overheads, lower watermark embedding and extraction cost, as well as higher security strength, compared to the previously proposed methods.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .D39. Source: Masters Abstracts International, Volume: 43-03, page: 0929. Advisers: H. K. Kwan; H. Wu. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004
    corecore