Hardware/Software Codesign

The current state of the art technology in integrated circuits allows the incorporation of multiple processor cores and memory arrays, in addition to application specific hardware, on a single substrate. As silicon technology has become more advanced, allowing the implementation of more complex designs, systems have begun to incorporate considerable amounts of embedded software [3]. Thus it becomes increasingly necessary for the system designers to have knowledge on both hardware and software to make efficient design tradeoffs. This is where hardware/software codesign comes into existence

Fuzzy logic based energy and throughput aware design space exploration for MPSoCs

Multicore architectures were introduced to mitigate the issue of increase in power dissipation with clock frequency. Introduction of deeper pipelines, speculative threading etc. for single core systems were not able to bring much increase in performance as compared to their associated power overhead. However for multicore architectures performance scaling with number of cores has always been a challenge. The Amdahl's law shows that the theoretical maximum speedup of a multicore architecture is not even close to the multiple of number of cores. With less amount of code in parallel having more number of cores for an application might just contribute in greater power dissipation instead of bringing some performance advantage. Therefore there is a need of an adaptive multicore architecture that can be tailored for the application in use for higher energy efficiency. In this paper a fuzzy logic based design space exploration technique is presented that is targeted to optimize a multicore architecture according to the workload requirements in order to achieve optimum balance between throughput and energy of the system

A template-based methodology for efficient microprocessor and FPGA accelerator co-design

Embedded applications usually require Software/Hardware (SW/HW) designs to meet the hard timing constraints and the required design flexibility. Exhaustive exploration for SW/HW designs is a very time consuming task, while the adhoc approaches and the use of partially automatic tools usually lead to less efficient designs. To support a more efficient codesign process for FPGA platforms we propose a systematic methodology to map an application to SW/HW platform with a custom HW accelerator and a microprocessor core. The methodology mapping steps are expressed through parametric templates for the SW/HW Communication Organization, the Foreground (FG) Memory Management and the Data Path (DP) Mapping. Several performance-area tradeoff design Pareto points are produced by instantiating the templates. A real-time bioimaging application is mapped on a FPGA to evaluate the gains of our approach, i.e. 44,8% on performance compared with pure SW designs and 58% on area compared with pure HW designs

Hardware/Software Partitioning of Floating Point Software Applications to Fixed-Pointed Coprocessor Circuits

ABSTRACT General Terms Design, Performance. Keywords Hardware/software partitioning, floating point to fixed conversion, floating point, fixed point

Interface configurable pour un processeur ARM basée sur le protocole VCI

Revue des méthodologies de conception de SOC -- Syntèse et raffinement d'une spécification de haut niveau -- Architecture et normes de SoC -- Possibilités de réutilisation des IP -- Méthodologie proposée et définition du projet -- Méthodologie de conception de SoC -- Description des caractéristiques de l'interface -- Utilisation de l'interface -- Analyse du design de l'Interface -- Choix d'implémentation -- Registres d'interruptions -- Commutateur -- Interface esclave -- Interface maître -- Algorithme de filtrage -- Algorithme d'encodage et de décodage Reed Solomon -- Algorithme du tri par segmentation