Design and Performance Analysis of a Non-Standard EPICS Fast Controller

The large scientific projects present new technological challenges, such as the distributed control over a communication network. In particular, the middleware EPICS is the most extended communication standard in particle accelerators. The integration of modern control architectures in these EPICS networks is becoming common, as for example for the PXI/PXIe and xTCA hardware alternatives. In this work, a different integration procedure for PXIe real time controllers from National Instruments is proposed, using LabVIEW as the design tool. This methodology is considered and its performance is analyzed by means of a set of laboratory experiments. This control architecture is proposed for achieving the implementation requirements of the fast controllers, which need an important amount of computational power and signal processing capability, with a tight real-time demand. The present work studies the advantages and drawbacks of this methodology and presents its comprehensive evaluation by means of a laboratory test bench, designed for the application of systematic tests. These tests compare the proposed fast controller performance with a similar system implemented using an standard EPICS IOC provided by the CODAC system.Comment: This is the extended version of the Conference Record presented in the IEEE Real-Time Conference 2014, Nara, Japan. This paper has been submitted to the IEEE Transactions on Nuclear Scienc

LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing

LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC.Peer ReviewedPostprint (author's final draft

GSFC Annual Scan Technology Review SpaceCube On-Board Processor Update

No abstract availabl

Digital signal processing: the impact of convergence on education, society and design flow

Design and development of real-time, memory and processor hungry digital signal processing systems has for decades been accomplished on general-purpose microprocessors. Increasing needs for high-performance DSP systems made these microprocessors unattractive for such implementations. Various attempts to improve the performance of these systems resulted in the use of dedicated digital signal processing devices like DSP processors and the former heavyweight champion of electronics design – Application Specific Integrated Circuits. The advent of RAM-based Field Programmable Gate Arrays has changed the DSP design flow. Software algorithmic designers can now take their DSP algorithms right from inception to hardware implementation, thanks to the increasing availability of software/hardware design flow or hardware/software co-design. This has led to a demand in the industry for graduates with good skills in both Electrical Engineering and Computer Science. This paper evaluates the impact of technology on DSP-based designs, hardware design languages, and how graduate/undergraduate courses have changed to suit this transition

Smart technologies for effective reconfiguration: the FASTER approach

Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows