On-Line Dependability Enhancement of Multiprocessor SoCs by Resource Management

This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

SiOx-based resistive switching memory integrated in nanopillar structure fabricated by nanosphere lithography

textA highly compact, one diode-one resistor (1D-1R) SiOx-based resistive switching memory device with nano-pillar architecture has been achieved for the first time using nano-sphere lithography. The average nano-pillar height and diameter are 1.3 μm and 130 nm, respectively. Low-voltage electroforming using DC bias and AC pulse response in the 50ns regime demonstrate good potential for high-speed, low-energy nonvolatile memory. Nano-sphere deposition, oxygen-plasma isolation, and nano-pillar formation by deep-Si-etching are studied and optimized for the 1D-1R configurations. Excellent electrical performance, data retention and the potential for wafer-scale integration are promising for future non-volatile memory applications.Materials Science and Engineerin

Experimental and theoretical study of ultra-thin oxides

We report on an experimental and theoretical study of transport through thin oxides. The experimental study was carried out on the tunnel switch diode (TSD) which consists of an MOS junction on top of a pn junction. The properties of the TSD depends critically on the properties of the tunnel oxide layer. Our results indicate that these devices can exhibit two different modes of behaviour depending on the stress history of the oxide. An unstressed device exhibits a thyristor-like I-V characteristic with fairly low current density. As the oxide is stressed, however, the I-V characteristic discontinuously shifts into a higher-current thyristor-like mode in which current transport appears to be highly non-uniform and depends strongly on stress history. This suggests a possible structural change in the oxide layer which is not completely destructive in that the device continues to function. We present a possible theoretical model of such a structural change in which microscopic filaments are generated in the oxide. Calculations of J-V curves for such structures with varying filament heights qualitatively match stressed MOS I-V curves found in the literature and qualitatively explain the dual-mode behaviour of the TSD

Configurable 3D-integrated focal-plane sensor-processor array architecture

A mixed-signal Cellular Visual Microprocessor architecture with digital processors is described. An ASIC implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face-to-face type integration, and one or several cascaded array of mainly identical (SIMD) processing elements. The individual array elements derived from the same general HDL description and could be of different in size, aspect ratio, and computing resources

An Automated System for Chromosome Analysis

The design, construction, and testing of a complete system to produce karyotypes and chromosome measurement data from human blood samples, and to provide a basis for statistical analysis of quantitative chromosome measurement data are described

Magnetic and electric field meters developed for the US Department of Energy

This report describes work done at the Jet Propulsion Laboratory for the Office of Energy Storage and Distribution of DOE on the measurement of power line fields. A magnetic field meter is discussed that uses fiber optics to couple a small measuring probe to a remote readout device. The use of fiber optics minimizes electric field perturbation due to the presence of the probe and provides electric isolation for the probe, so that it could be used in a high field or high voltage environment. Power to operate the sensor electronics is transferred via an optical fiber, and converted to electrical form by a small photodiode array. The fundamental, the second and third harmonics of the field are filtered and separately measured, as well as the broadband rms level of the field. The design of the meter is described in detail and data from laboratory tests are presented. The report also describes work done to improve the performance of a DC bushing in a Swedish factory, using the improved meter. The DC electric fields are measured with synchronous detection to provide field magnitude data in two component directions