System efficient ESD design concept for soft failures

This research covers the topic of developing a systematic methodology of studying electrostatic discharge (ESD)-induced soft failures. ESD-induced soft failures (SF) are non-destructive disruptions of the functionality of an electronic system. The soft failure robustness of a USB3 Gen 1 interface is investigated, modeled, and improved. The injection is performed directly using transmission line pulser (TLP) with varying: pulse width, amplitude, polarity. Characterization provides data for failure thresholds and a SPICE circuit model that describes the transient voltage and current at the victim. Using the injected current, the likelihood of a SF is predicted. ESD protection by transient voltage suppressor (TVS) diodes is numerically simulated in several configurations. The results strongly suggest the viability of using well-established hard failure mitigation techniques for improving SF robustness, and the possibility of using numerical simulation for optimization purposes. A concept of soft failure system efficient ESD design (SF-SEED) is proposed and shown to be effective --Abstract, page iv

ESD Behavior of RF Switches and Importance of System Efficient ESD Design

RF Switches Are Typically Used in the RF Front-End of Portable Devices Such as Antenna or Matching Tuners to Improve the RF Link Performance. They Are Usually the First Active Devices after the Antenna and Are Vulnerable to Primary or Secondary ESD Discharges to the Antennas. This Paper Investigates the ESD Behavior of One of the High Frequency Switches Used in the RF-Front-End of Portable Devices and Expresses the Importance of the ESD Pulse that Passes through the Switch and Reaches the Next Stage in the RF Path, Possibly Damaging the Next Stage

Optimization and modeling of ESD protection devices

“Transient voltage suppressors (TVS) are used to protect ICs (integrated circuits) against overvoltage, ESD (Electrostatic Discharge), inductive load switching, and even lightning strikes. In this research, a transient behavior model framework for ESD protection devices is used for modelling four different types of TVS (non-snapback, snapback, spark gap like device and varistor). The System-Efficient ESD Design (SEED) methodology is utilized to strengthen the trust in the model framework by efficient simulation of ESD interaction of the off-chip ESD protection devices with the IC ESD protection device and associated measurement data. Improvements in the TVS transient response, accounting for conductivity modulation, voltage overshot at the snapback voltage, etc., are required to accurately model the ESD protection device. With this in mind, the unimproved model is presented for various ESD protection device where their transient behavior of single component can be fully described by a quasistatic very fast transmission line pulse (VF)-TLP. The improved model is validated within a sub-system consisting of an off-chip ESD protection device, an IC on-chip protection and a PCB trace in between. Multiple solutions to avoid convergence issues are also proposed for effective simulation”--Abstract, page iv

SEED modeling of an ESD gun discharge to a USB cable

“An IC protected by a transient voltage suppression (TVS) diode may fail if the TVS device does not turn on or does not turn on quickly enough, causing the IC to take the full brunt of the electrostatic discharge (ESD) event. Transient simulation models have been developed for ESD protection devices for the purpose of system-efficient ESD design (SEED). The TVS modeling methodology has been improved to better represent the physics that occurs during the TVS response and more accurately predict the interactions between off-chip and on-chip protection devices. Moreover, a complicated test scenario -- an ESD gun discharge through a USB cable -- was investigated and simulated, to demonstrate the impact of position, grounding condition, and quality of the USB cable. Test and design guidelines are proposed for incorporating a USB cable in a contact-discharge ESD test. At the beginning, a hybrid simulation approach was proposed, which uses a full-wave model of the ESD gun, cable, and enclosure combined with the ESD protection devices and test board’s circuit-level models. The voltage and current of ESD protection devices are captured within 24-35% compared to the measurements, under various cable configurations. To further improve the simulation accuracy, physics-based modeling methodologies were proposed to improve the previously developed TVS model, especially on the falling edge after the overshoot. The ESD protection device’s response was studied in simulation and measurement for various cable configurations. And the overall discrepancy is within 30%. The modeling process can help engineers to evaluate the design effectiveness under various complicated test scenarios”--Abstract, page iv

Characterization and modeling of ESD events, risk and protection

“The ESD (Electrostatic discharge) failures have been raising critical reliability problems in electronic devices design. However, not all the ESD scenarios have been specified by the IEC standard and the characterizations of the ESD risk for different scenarios are essential to evaluate the ESD robustness of the devices in the real word. The insulation of plastic enclosures provides protection against ESD to the electronic system inside. However, seams between plastic parts are often unavoidable. Different plastic arrangements are constructed to investigate the spark length and current derivatives and to understand the ESD spark behavior for geometries having spark lengths longer than the values predicted by Paschen’s law. For the wearable devices, the core difference between the posture assumed for IEC 61000-4-2 human metal discharge and a discharge to a wearable device is the impedance between the charged body and the grounded structure discharged to. The results show that the current measured in the brush-by scenario can reach values twice as high as the current specified in the IEC standard. A simulation model using the measured impedance and Rompe and Weizel’s law provides predictions on the peak current derivative when the spark length is varied. The increasing peak current derivative with shorter spark length indicates stronger field coupling to the devices. SEED(System-efficient ESD design) modeling helps the designer to predict the ESD risk at the early stage, an accurate TVS model can be used to study the transient response of the external TVS and the on-chip protection when applied in a typical high-speed input/output (I/O) interface”--Abstract, page iv

Application of TVS Models for SEED Simulation of a Variety of TVS Devices

Accurate Models of Transient Voltage Suppression (TVS) Devices Are Important for Determining the Suitability of Electrostatic Discharge (ESD) Protection Strategies Early in the Design Process. an Improved TVS Model is Used in the Following Paper to Represent a Variety of TVS Devices, Including a Snapback Device, Non-Snapback Device, and a Varistor. the Models Include Recent Improvements to Represent Conductivity Modulation and the overall Shape of the TVS Device\u27s Transient Response. the Models Are Tuned based on Characterizations of These Protection Devices using a Transmission Line Pulse (TLP) and Are Then Used in a System Efficient ESD Design (SEED) Simulation to Predict the Transient Voltages and Currents in a System Consisting of an Off-Chip TVS, an IC with On-Chip ESD Protection, and a PCB Trace in Between. Simulated Transient Voltage and Current Waveforms Closely Match Measurements Both When Testing the TVS Devices by Themselves and in SEED Simulations. Peak and Quasistatic Currents through the TVS and On-Chip Diode Were Typically Captured within About 10% or Less Across the Devices Tested While Varying Both the Rise Time and Level of the Injected TLP

High-voltage ESD structures and ESD protection concepts in smart power technologies

Electro-static discharge (ESD) event can cause upset or permanent damage of integrated circuits (IC) and electrical systems. The risk of ESD fails needs to be mitigated or prevented. ESD robustness of IC products and electrical systems is specified, verified and qualified according to respective ESD standards. For high-voltage IC products based on smart power semiconductor technologies for industrial, power and automotive applications, design of effective and cost-efficient ESD protection is a big challenge, demanding wide and deep technical knowledge throughout high-frequency and high-power characterization techniques, semiconductor device physic, circuit design as well as modeling and simulation. The required measurement setups and tester components are developed and introduced. The characterization of ESD protection devices, IC and off-chip circuit elements is enabled and improved. The rise-time filters are important for the study of rise-time dependent ESD robustness. The human metal model (HMM) tester as an alternative to IEC ESD generators provides voltage waveform measurement with good quality in addition to current waveform measurement. It can be used for wafer-level or package-level device characterization. The measurement results of HMM tester and IEC ESD generator are compared. The on-chip ESD protection design relies on proper choice of different types of ESD protection devices and structures, depending on ESD specifications and IC applications. Typical on-chip ESD protection, whether snapback or non-snapback, single device or ESD circuit is introduced. The failure levels studies give a systematic benchmark of the ESD protection devices and structures, concerning device area, clamping voltage and other relevant parameters. The trade-off between those parameters and limitation of different ESD protection is discussed. Moreover, understanding of ESD failure modes is the key to implement effective ESD design. A unique ESD failure mode of smart power semiconductor device is discovered and investigated in detail. In the scope of finding ESD solutions, new active ESD clamps have been further developed in this work. The study of ESD protection is extended to the system-level involving on- and off-chip ESD protection elements. The characteristics of typical off-chip elements as well as the interaction between IC and off-chip protection elements plays essential role on the system robustness. A system-level ESD simulation incorporating IC and off-chip protection elements is desired for system efficient ESD design (SEED). A behavioral ESD model is developed which reproduces pulse-energy-dependent failure levels and self-heating effects. This modeling methodology can be used for assessment of system robustness even beyond ESD time-domain. The validation of the models is given by representative application examples. Several main challenges of high-voltage ESD design in smart power technologies have been addressed in this work, which can serve as guidance for ESD development and product support in future power semiconductor technologies

Implementing Energy Efficiency & ESD from a Development Perspective

This note discusses the difficulties currently being experienced in implementing Ecological Sustainable Development (ESD) from a development perspective. It looks at what motivates developers and examines what is needed, either through mandatory measures or incentives to change the development culture in Australia. The note draws on experience from a number of current and recently completed projects and incorporates input from developers. It also includes discussion on the evolving outcomes of current industry initiatives aimed specifically at changing development processes and culture in Australia. The note focuses on new buildings. The way in which new buildings are financed and delivered generally differs significantly from retrofit projects being undertaken by building owners. Building owners can more easily factor long term operational costs of their buildings into their retrofit project financing. Typically, building developers are not the long-term owners, operators or tenants of the buildings that they deliver. Their projects are normally sold before or soon after completion to unrelated parties such as property trusts, superannuation funds, and other investors. It is this discontinuity in development and ownership of new buildings that creates perhaps the single biggest challenge to the uptake of ESD for the property industry

On-Chip ESD Protection Design: Optimized Clamps

The extensive use of Integrated Circuits (ICs) means complex working conditions for these tiny chips. To guarantee the ICs could work properly in various environments, some special protection strategies are required to improve the reliability of system. From all the possible reliability issues, the electrostatics discharge (ESD) might be the most common one. The peak current of electrostatics can be as high as tens of amperes and the peak voltage can be over thousand voltages. In contrast, the size of semiconductor device fabricated is continuing to scale down, making it even more vulnerable to high level overstress and current surge induced by ESD event. To protect the on-chip semiconductor from damage, some extra clamp cells are put together to consist a network. The network can redirect the superfluous current through the ESD network and clamp the voltage to a low level. In this dissertation, one design concept is introduced that uses the combination of some basic ESD devices to meet different requirements first, and then tries to establish parasitic current path among these devices to further increase the current handling capability. Some design cases are addressed to demonstrate this design concept is valid and efficient: 1. A combination of silicon-controlled-rectifier (SCR) and diode cluster is implemented to resolve the overshoot issue under fast ESD event. 2. A new SCR structure is introduced, which can be used as padding device to increase the clamping voltage without affecting other parameters. Based on this padding device, two design cases are introduced. 3. A controllable SCR clamp structure is presented, which has high current handling capability and can be controlled with by small signal. All these structures and topologies described in this dissertation are compatible with most of popular semiconductor fabrication process

Evaluation of the practicality of system efficient ESD design

A custom test board facilitates transmission line pulse (TLP) characterization of the external pins of an integrated circuit. Models extracted from the data are used to simulate the pin level response of the integrated circuit (IC) to an IEC 61000-4-2 discharge. Electrostatic discharge (ESD) gun zaps are applied to the test board; simulated and measured waveforms are compared