FPGAs in Industrial Control Applications

The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications. Authors start by addressing various research fields which can exploit the advantages of FPGAs. The features of these devices are then presented, followed by their corresponding design tools. To illustrate the benefits of using FPGAs in the case of complex control applications, a sensorless motor controller has been treated. This controller is based on the Extended Kalman Filter. Its development has been made according to a dedicated design methodology, which is also discussed. The use of FPGAs to implement artificial intelligence-based industrial controllers is then briefly reviewed. The final section presents two short case studies of Neural Network control systems designs targeting FPGAs

Design And Fabrication Of A Microchip To Generate Sequential Pulse Output For Artificial Skin Sensor Array

University of Minnesota M.S.E.E. thesis. 2016. Major: Electrical Engineering. Advisor: Jing Bai. 1 computer file (PDF); 86 pages.In this project, we have designed and implemented the circuit, which basically generates sequential shifted pulse sequences. The circuit is a part of the pressure sensor system for colonoscopy. The other parts of the sensing system include the artificial skin sensor array and a data acquisition (DA) system. The circuit will be connected with sensor array to detect the signal at each dot of the sensing array grid. The artificial skin sensor array has been designed by our research partner in MIE department. The designed circuit will be integrated with the pressure sensor array to convert the pressure value into electrical signal, which should be readable from the computer terminal through a DA System. The designed circuit is expected to provide multiple outputs from a single input signal. Each output should be distinguishable. The work we reported in this thesis is the second version of the circuit design. The circuit designed in the first version has the problem of too much offset from our expected output. In this version, we improved this through adding additional noises and offset. We implemented the designed circuit on both breadboard and printed circuit board (PCB). Testing results on each board shows expected performance. In addition, we also made effort to fabricate the circuit on a microchip in order to minimize the size of the circuit and make it finally fit into the sensor system for practical application. We applied the very large scale integrated-circuit (VLSI) technique on the implementation of the microchip. We went through the procedure of creating the scheme of microchip fabrication through VLSI software Cadence® and verify the layout using Calibre® physical verification software. We used the free service from MOSIS, Inc for the fabrication process. The fabricated circuit is expected to arrive in a couple of months. Testing of the circuit will be one of our subsequent tasks of this project

FPGA design methodology for industrial control systems—a review

This paper reviews the state of the art of fieldprogrammable gate array (FPGA) design methodologies with a focus on industrial control system applications. This paper starts with an overview of FPGA technology development, followed by a presentation of design methodologies, development tools and relevant CAD environments, including the use of portable hardware description languages and system level programming/design tools. They enable a holistic functional approach with the major advantage of setting up a unique modeling and evaluation environment for complete industrial electronics systems. Three main design rules are then presented. These are algorithm refinement, modularity, and systematic search for the best compromise between the control performance and the architectural constraints. An overview of contributions and limits of FPGAs is also given, followed by a short survey of FPGA-based intelligent controllers for modern industrial systems. Finally, two complete and timely case studies are presented to illustrate the benefits of an FPGA implementation when using the proposed system modeling and design methodology. These consist of the direct torque control for induction motor drives and the control of a diesel-driven synchronous stand-alone generator with the help of fuzzy logic

Pipelined Asynchronous High Level Synthesis for General Programs

High-level synthesis (HLS) translates algorithms from software programming language into hardware. We use the dataflow HLS methodology to translate programs into asynchronous circuits by implementing programs using asynchronous dataflow elements as hardware building blocks. We extend the prior work in dataflow synthesis in the following aspects:i) we propose Fluid to synthesize pipelined dataflow circuits for real-world programs with complex control flows, which are not supported in the previous work; ii) we propose PipeLink to permit pipelined access to shared resources in the dataflow circuit. Dataflow circuit results in distributed control and an implicitly pipelined implementation. However, resource sharing in the presence of pipelining is challenging in this context due to the absence of a global scheduler. Traditional solutions to this problem impose restrictions on pipelining to guarantee mutually exclusive access to the shared resource, but PipeLink removes such restrictions and can generate pipelined asynchronous dataflow circuits for shared function calls, pipelined memory accesses and function pointers; iii) we apply several dataflow optimizations to improve the quality of the synthesized dataflow circuits; iv) we implement our system (Fluid + PipeLink) on the LLVM compiler framework, which allows us to take advantage of the optimization efforts from the compiler community; v) we compare our system with a widely-used academic HLS tool and two commercial HLS tools. Compared to commercial (academic) HLS tools, our system results in 12X (20X) reduction in energy, 1.29X (1.64X) improvement in throughput, 1.27X (1.61X) improvement in latency at a cost of 2.4X (1.61X) increase in the area

Compiling dataflow graphs into hardware

Department Head: L. Darrell Whitley.2005 Fall.Includes bibliographical references (pages 121-126).Conventional computers are programmed by supplying a sequence of instructions that perform the desired task. A reconfigurable processor is "programmed" by specifying the interconnections between hardware components, thereby creating a "hardwired" system to do the particular task. For some applications such as image processing, reconfigurable processors can produce dramatic execution speedups. However, programming a reconfigurable processor is essentially a hardware design discipline, making programming difficult for application programmers who are only familiar with software design techniques. To bridge this gap, a programming language, called SA-C (Single Assignment C, pronounced "sassy"), has been designed for programming reconfigurable processors. The process involves two main steps - first, the SA-C compiler analyzes the input source code and produces a hardware-independent intermediate representation of the program, called a dataflow graph (DFG). Secondly, this DFG is combined with hardware-specific information to create the final configuration. This dissertation describes the design and implementation of a system that performs the DFG to hardware translation. The DFG is broken up into three sections: the data generators, the inner loop body, and the data collectors. The second of these, the inner loop body, is used to create a computational structure that is unique for each program. The other two sections are implemented by using prebuilt modules, parameterized for the particular problem. Finally, a "glue module" is created to connect the various pieces into a complete interconnection specification. The dissertation also explores optimizations that can be applied while processing the DFG, to improve performance. A technique for pipelining the inner loop body is described that uses an estimation tool for the propagation delay of the nodes within the dataflow graph. A scheme is also described that identifies subgraphs with the dataflow graph that can be replaced with lookup tables. The lookup tables provide a faster implementation than random logic in some instances

High Frequency Devices and Circuit Modules for Biochemical Microsystems

This dissertation investigates high frequency devices and circuit modules for biochemical microsystems. These modules are designed towards replacing external bulky laboratory instruments and integrating with biochemical microsystems to generate and analyze signals in frequency and time domain. The first is a charge pump circuit with modified triple well diodes, which is used as an on-chip power supply. The second is an on-chip pulse generation circuit to generate high voltage short pulses. It includes a pulse-forming-line (PFL) based pulse generation circuit, a Marx generator and a Blumlein generator. The third is a six-port circuit based on four quadrature hybrids with 2.0~6.0 GHz operating frequency tuning range for analyzing signals in frequency domain on-chip. The fourth is a high-speed sample-and-hold circuit (SHC) with a 13.3 Gs/s sampling rate and ~11.5 GHz input bandwidth for analyzing signals in time domain on-chip. The fifth is a novel electron spin resonance (ESR) spectroscopy with high-sensitivity and wide frequency tuning range

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Space Communications: Theory and Applications. Volume 3: Information Processing and Advanced Techniques. A Bibliography, 1958 - 1963

Annotated bibliography on information processing and advanced communication techniques - theory and applications of space communication

Controlling and Processing Core for Wireless Implantable Telemetry System

Wireless implantable telemetry systems are suitable choices for monitoring various physiological parameters such as blood pressure and volume. These systems typically compose of an internal device implanted into a living body captures the physiological data and sends them to an external base station located outside of the body for further processing. The internal device usually consists of a sensor interface to convert the collected data to electrical signals; a digital core to digitize the analog signals, process them and prepare them for transmission; an RF front-end to transmit the data outside the body and to receive the required commands from the end station; and a wireless power supply. The digital core plays an important role in these systems since the data must be digitized and processed before transmitting to the end station for further processing. In this thesis, we presented an FPGA-based prototype for controlling and processing core of a miniature implantable telemetry system that is used to monitoring physiological parameters of laboratory small animals. The presented module samples and digitizes the collected data using an analog to digital converter, stores the collected data, generates the controlling output commands, processing the received data, and controls the power consumption of the system. The circuit is prototyped and experimentally verified using an FPGA development platform, then synthesized and simulated in 130 nm CMOS IC technology using standard digital cells. The overall core design occupies 1.6 mm × 1.6 mm CMOS area, and consumes 14.5 mW (IC) or 208 mW (FPGA) total power