An Enhanced Hardware Description Language Implementation for Improved Design-Space Exploration in High-Energy Physics Hardware Design

Detectors in High-Energy Physics (HEP) have increased tremendously in accuracy, speed and integration. Consequently HEP experiments are confronted with an immense amount of data to be read out, processed and stored. Originally low-level processing has been accomplished in hardware, while more elaborate algorithms have been executed on large computing farms. Field-Programmable Gate Arrays (FPGAs) meet HEP's need for ever higher real-time processing performance by providing programmable yet fast digital logic resources. With the fast move from HEP Digital Signal Processing (DSPing) applications into the domain of FPGAs, related design tools are crucial to realise the potential performance gains. This work reviews Hardware Description Languages (HDLs) in respect to the special needs present in the HEP digital hardware design process. It is especially concerned with the question, how features outside the scope of mainstream digital hardware design can be implemented efficiently into HDLs. It will argue that functional languages are especially suitable for implementation of domain-specific languages, including HDLs. Casestudies examining the implementation complexity of HEP-specific language extensions to the functional HDCaml HDL will prove the viability of the suggested approach

The Design of an asynchronous VHDL synthesizer

Abstract This paper presents a straightforward approach for synthesizing a standard VHDL description of an asynchronous circuit from a behavioural VHDL description. The asynchronous circuit style is based on`micropipelines', a style currently used to develop asynchronous microprocessors at Manchester University. The rules of partition and conversion which are used to implement the synthesizer are also described. The synthesizer greatly reduces the design time of a complex micropipeline circuit

A low power design for arithmetic and logic unit

Master'sMASTER OF ENGINEERIN

The BRAIN Initiative: developing technology to catalyse neuroscience discovery

The evolution of the field of neuroscience has been propelled by the advent of novel technological capabilities, and the pace at which these capabilities are being developed has accelerated dramatically in the past decade. Capitalizing on this momentum, the United States launched the Brain Research through Advancing Innovative Neurotechnologies (BRAIN) Initiative to develop and apply new tools and technologies for revolutionizing our understanding of the brain. In this article, we review the scientific vision for this initiative set forth by the National Institutes of Health and discuss its implications for the future of neuroscience research. Particular emphasis is given to its potential impact on the mapping and study of neural circuits, and how this knowledge will transform our understanding of the complexity of the human brain and its diverse array of behaviours, perceptions, thoughts and emotions

HIGH-LEVEL SYNTHESIS USING PREDEFINED IP-S

In this paper, an algorithm is presented for decomposing a system into IP (Intellectual Property) functional units. The system to be decomposed is characterized by a complete cover of the set of its behavioral datapath operations. Such a cover is obtainable at the allocation stage of a high-level synthesis procedure. Each block of the cover represents a subset of behavioral operations, which are non-concurrent, i.e., are executable by the same real resource (processor). Each IP - as a real resource - is assumed to be specified also by a subset of behavioral operations, the execution of which is possible and preferred by applying this IP. The quality constraints of the decomposition are handled as a weighted composition of several criteria, which may characterize a solution (degree of reuse, weighted sum of several cost parameters, etc.). Since the problem is NP-complete \citeDeMicheli94, the quality of the results is illustrated and evaluated on a widely used benchmark example of practical size