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Design of a 3 GHz fine resolution LC DCO
In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning. Both delta-sigma modulator and capacitive divider circuit are implemented to achieve a finer resolution and a larger dynamic range. The LC-oscillator has a coarse tuning range from 3.05 GHz to 3.85 GHz and a fine tuning range of 50MHz. It features a phase noise level of -115dBc/Hz at 1MHz frequency offset and consumes 5.4mW. Efficient simulation methodology is explored. Finally, this DCO is simulated in an All-Digital Phase Locked Loop (ADPLL) with other ideal behavior blocks implemented using Verilog-A, and the performance of the DCO is evaluated.Electrical and Computer Engineerin
Lyapunov-like Conditions of Forward Invariance and Boundedness for a Class of Unstable Systems
We provide Lyapunov-like characterizations of boundedness and convergence of
non-trivial solutions for a class of systems with unstable invariant sets.
Examples of systems to which the results may apply include interconnections of
stable subsystems with one-dimensional unstable dynamics or critically stable
dynamics. Systems of this type arise in problems of nonlinear output
regulation, parameter estimation and adaptive control.
In addition to providing boundedness and convergence criteria the results
allow to derive domains of initial conditions corresponding to solutions
leaving a given neighborhood of the origin at least once. In contrast to other
works addressing convergence issues in unstable systems, our results require
neither input-output characterizations for the stable part nor estimates of
convergence rates. The results are illustrated with examples, including the
analysis of phase synchronization of neural oscillators with heterogenous
coupling
Design of Power Optimized circuit of LC Voltage Controlled Oscillator for use in GSM Handsets
The recent performance requirements for mobile phones have been extending its area of interest. Handsets need to have high resolution graphics, pictures, and applications. Consequently, the requirement for a longer battery life has become a bare necessity. This makes optimization of power a critical issue. Along with this cell phones need to be thin and have light weight.
A major portion of the power consumption of the handsets can be attributed to the LC oscillators used in the system. A Voltage Controlled Oscillator plays an important role in any communication system. It provides the frequency signal for down-conversion of input signals and also the carrier signals for the modulating signal.
Proper amplitude and low phase noise are two important criteria to achieve suitable performance for a VCO in any transceiver system. The strong combination of low phase noise specifications with very low power consumption (battery operation) forces designers to use LC-VCOs. A great research effort has been done in the design of integrated voltage controlled oscillators (VCOs) using integrated or external resonators, but as their power consumption still cannot be unacceptable, today’s mobile phones commonly use external LC-VCO modules.
Inductors used in these oscillators are usually bulky and have high power consumption. The low power LC oscillator increases the standby time, thus improving the battery life. Extended battery life provides processing power at lower clock speeds, enabling low leakage process that optimizes power consumption and increases battery time. Also provides integrated and sophisticated systems with improved power management.
The main purpose of this project is to design a circuit for LC VCO to be used in GSM system with a tuning rage of 3-4GHz. Since the phase noise requirement for the system is less than 150dBc/Hz at 20 KHz offset. Also for a GSM system, the size of the inductor used in the oscillator is a major issue in determining its overall size, efforts will be made to optimize the size of the inductor as well
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