A Particle Swarm Optimization Technique used for the Improvement of Analogue Circuit Performances

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On-chip Voltage Regulator– Circuit Design and Automation

Title from PDF of title page viewed May 24, 2021Dissertation advisors: Masud H Chowdhury and Yugyung LeeVitaIncludes bibliographical references (page 106-121)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2021With the increase of density and complexity of high-performance integrated circuits and systems, including many-core chips and system-on-chip (SoC), it is becoming difficult to meet the power delivery and regulation requirements with off-chip regulators. The off-chip regulators become a less attractive choice because of the higher overheads and complexity imposed by the additional wires, pins, and pads. The increased I2R loss makes it challenging to maintain the integrity of different voltage domains under a lower supply voltage environment in the smaller technology nodes. Fully integrated on-chip voltage regulators have proven to be an effective solution to mitigate power delivery and integrity issues. Two types of regulators are considered as most promising for on-chip implementation: (i) the low-drop-out (LDO) regulator and (ii) the switched-capacitor (SC)regulator. The first part of our research mainly focused on the LDO regulator. Inspired by the recent surge of interest for cap-less voltage regulators, we presented two fully on-chip external capacitor-less low-dropout voltage regulator design. The second part of this proposal explores the complexity of designing each block of the regulator/analog circuit and proposed a design methodology for analog circuit synthesis using simulation and learning-based approach. As the complexity is increasing day-by-day in an analog circuit, hierarchical flow mostly uses for design automation. In this work, we focused mainly on Circuit-level, one of the significant steps in the flow. We presented a novel, efficient circuit synthesis flow based on simulation and learning-based optimization methods. The proposed methodology has two phases: the learning phase and the evaluation phase. Random forest, a supervised learning is used to reduce the sample points in the design space and iteration number during the learning phase. Additionally, symmetric constraints are used further to reduce the iteration number during the sizing process. We introduced a three-step circuit synthesis flow to automate the analog circuit design. We used H-spice as a simulation tool during the evaluation phase of the proposed methodology. The three most common analog circuits are chosen: single-stage differential amplifier, operational transconductance amplifier, and two-stage differential amplifier to verify the algorithm. The tool is developed in Python, and the technology we used is0.6um. We also verified the optimized result in Cadence Virtuoso.Introduction -- On-chip power delivery system -- Fundamentals of on-chip voltage regulator -- LDO design in 45NM technology -- LDO design in technology -- Analog design automation -- Proposed analog design methodology -- Energy efficient FDSOI and FINFET based power gating circuit using data retention transistor -- Conclusion and future wor

VLSI analogs of neuronal visual processing: a synthesis of form and function

This thesis describes the development and testing of a simple visual system fabricated using complementary metal-oxide-semiconductor (CMOS) very large scale integration (VLSI) technology. This visual system is composed of three subsystems. A silicon retina, fabricated on a single chip, transduces light and performs signal processing in a manner similar to a simple vertebrate retina. A stereocorrespondence chip uses bilateral retinal input to estimate the location of objects in depth. A silicon optic nerve allows communication between chips by a method that preserves the idiom of action potential transmission in the nervous system. Each of these subsystems illuminates various aspects of the relationship between VLSI analogs and their neurobiological counterparts. The overall synthetic visual system demonstrates that analog VLSI can capture a significant portion of the function of neural structures at a systems level, and concomitantly, that incorporating neural architectures leads to new engineering approaches to computation in VLSI. The relationship between neural systems and VLSI is rooted in the shared limitations imposed by computing in similar physical media. The systems discussed in this text support the belief that the physical limitations imposed by the computational medium significantly affect the evolving algorithm. Since circuits are essentially physical structures, I advocate the use of analog VLSI as powerful medium of abstraction, suitable for understanding and expressing the function of real neural systems. The working chip elevates the circuit description to a kind of synthetic formalism. The behaving physical circuit provides a formal test of theories of function that can be expressed in the language of circuits

Synthesis and monolithic integration of analogue signal processing networks

Data traffic of future 5G telecommunication systems is projected to increase 10 000-fold compared to current rates. 5G fronthaul links are therefore expected to operate in the mm-wave spectrum with some preliminary International Telecommunication Union specifications set for the 71-76 and 81-86 GHz bands. Processing 5 GHz as a single contiguous band in real-time, using existing digital signal processing (DSP) systems, is exceedingly challenging. A similar challenge exists in radio astronomy, with the Square Kilometer Array project expecting data throughput rates of 15 Tbits/s at its completion. Speed improvements on existing state-of-the-art DSPs of 2-3 orders of magnitude are therefore required to meet future demands. One possible mitigating approach to processing wideband data in real-time is to replace some DSP blocks with analog signal processing (ASP) equivalents, since analogue devices outperform their digital counterparts in terms of cost, power consumption and the maximum attainable bandwidth. The fundamental building block of any ASP is an all-pass network of prescribed response, which can always be synthesized by cascaded first- and second-order all-pass sections (with two cascaded first-order sections being a special case of the latter). The monolithic integration of all-pass networks in commercial CMOS and BiCMOS technology nodes is a key consideration for commercial adaptation of ASPs, since it supports mass production at reduced costs and operating power requirements, making the ASP approach feasible. However, this integration has presented a number of yet unsolved challenges. Firstly, the state-of-the-art methods for synthesizing quasi-arbitrary group delay functions using all-pass elements lack a theoretical synthesis procedure that guarantees minimum-order networks. In this work an analytically-based solution to the synthesis problem is presented that produces an all-pass network with a response approximating the required group delay to within an arbitrary minimax error. This method is shown to work for any physical realization of second-order all-pass elements, is guaranteed to converge to a global optimum solution without any choice of seed values as an input, and allows synthesis of pre-defined networks described either analytically or numerically. Secondly, second-order all-pass networks are currently primarily implemented in off-chip planar media, which is unsuited for high volume production. Component sensitivity, process tolerances and on-chip parasitics often make proposed on-chip designs impractical. Consequently, to date, no measured results of a dispersive on-chip second-order all-pass network suitable for ASP applications (delay Q-value (QD) larger than 1) have been presented in either CMOS or BiCMOS technology nodes. In this work, the first ever on-chip CMOS second-order all-pass network is proposed with a measured QD-value larger than 1. Measurements indicate a post-tuning bandwidth of 280 MHz, peak-to-nominal delay variation of 10 ns, QD-value of 1.15 and magnitude variation of 3.1 dB. An active on-chip mm-wave second-order all-pass network is further demonstrated in a 130 nm SiGe BiCMOS technology node with a bandwidth of 40 GHz, peak-to-nominal delay of 62 ps, QD-value of 3.6 and a magnitude ripple of 1.4 dB. This is the first time that measurement results of a mm-wave bandwidth second-order all-pass network have been reported. This work therefore presents the first step to monolithically integrating ASP solutions to conventional DSP problems, thereby enabling ultra-wideband signal processing on-chip in commercial technology nodes.Thesis (PhD)--University of Pretoria, 2018.Square Kilometer Array (SKA) project - postgraduate scholarshipElectrical, Electronic and Computer EngineeringPhDUnrestricte

General rational approximation of Gaussian wavelet series and continuous-time gm-C filter implementation

© 2020 John Wiley & Sons, Ltd. This is the accepted version of the following article: Li, M, Sun, Y. General rational approximation of Gaussian wavelet series and continuous‐time g m ‐C filter implementation. Int J Circ Theor Appl. 2020; 1– 17., which has been published in final form at https://doi.org/10.1002/cta.2834.A general method of rational approximation for Gaussian wavelet series and Gaussian wavelet filter circuit design with simple gm-C integrators is presented in this work. Firstly, the multi-order derivatives of Gaussian function are analysed and proved as wavelet base functions. Then a high accuracy general approximation model of Gaussian wavelet series is constructed and the transfer function of first order derivative of Gaussian wavelet filter is obtained using quantum differential evolution (QDE) algorithm. Thirdly, as an example, a 5th order continuous-time analogue first order derivative of Gaussian wavelet filter circuit is designed based on multiple loop feedback structure with simple gm-C integrator as the basic blocks. Finally, simulation results demonstrate the proposed method is an excellent way for the wavelet transform implementation. The designed first order derivative of Gaussian wavelet filter circuit operates from a 0.53V supply voltage and a bias current 2.5nA. The power dissipation of the wavelet filter circuit at the basic scale is 41.1nW. Moreover, the high accuracy QRS detection based on the designed wavelet filter has been validated in application analysis.Peer reviewe

Analog VLSI Phototransduction by continuous-time, adaptive, logarithmic photoreceptor circuits

Over the last few years, we and others have built a number of interesting neuromorphic analog vision chips that do focal-plane time-domain computation. These chips do local, continuous-time, spatiotemporal processing that takes place before any sampling or long-range communication, for example, motion processing, change detection, neuromorphic retinal preprocessing, stereo image matching, and synthesis of auditory images from visual scenes. This processing requires photoreceptor circuits that transduce from light falling on the chip to an electrical signal. If we want to build analog vision chips that do high-quality focal plane processing, then we need good photoreceptors. It's not enough to just demonstrate a concept; ultimate usefulness will be determined by market forces, which, among other factors, depend a lot on raw performance. The receptor circuits we discuss here have not been used in any commercial product, so they have not yet passed that most crucial test, but by every performance metric we can come up with, including successful fabrication and test of demonstration systems, they match performance criteria met by other phototransduction techniques that are used in end-product consumer electronic devices. We hope that this article will serve several purposes: We want people to have a reference where they can look to see the functioning and practical problems of phototransducers built in a typical CMOS or BiCMOS process. We want to inspire people to build low-power, integrated commercial vision devices for practical purposes. We want to provide a photoreceptor that can be used as a front end transducer in more advanced research on neuromorphic systems. The transduction process seems mundane, but it is important --GIGO comes to mind. Subsequent computation relies on the information. We don't know of any contemporary (VLSI-era) literature that comprehensively explore the subject. Previous results are lacking in some aspect, either in the circuit itself, or in the understanding of the physics, or in the realistic measurement of limitations on behavior. We'll focus on one highly-evolved adaptive receptor circuit to understand how it operates, what are the limitations on its dynamic range, and what is the physics of the noise behavior. The receptor has new and previously unpublished technical improvements, and we understand the noise properties and illumination limits much better than we did before. We'll also discuss the practical aspects of the interaction of light with silicon: What are the spectral responses of various devices? How far do light-generated minority carriers diffuse and how do they affect circuit operation? How effective are guard bars to protect against them? Finally, we'll talk about biological receptors: How do their functional characteristics inspire the electronic model? How are the mechanisms of gain and adaptation related

Chemical Bionics - a novel design approach using ion sensitive field effect transistors

In the late 1980s Carver Mead introduced Neuromorphic engineering in which various aspects of the neural systems of the body were modelled using VLSI1 circuits. As a result most bio-inspired systems to date concentrate on modelling the electrical behaviour of neural systems such as the eyes, ears and brain. The reality is however that biological systems rely on chemical as well as electrical principles in order to function. This thesis introduces chemical bionics in which the chemically-dependent physiology of specific cells in the body is implemented for the development of novel bio-inspired therapeutic devices. The glucose dependent pancreatic beta cell is shown to be one such cell, that is designed and fabricated to form the first silicon metabolic cell. By replicating the bursting behaviour of biological beta cells, which respond to changes in blood glucose, a bio-inspired prosthetic for glucose homeostasis of Type I diabetes is demonstrated. To compliment this, research to further develop the Ion Sensitive Field Effect Transistor (ISFET) on unmodified CMOS is also presented for use as a monolithic sensor for chemical bionic systems. Problems arising by using the native passivation of CMOS as a sensing surface are described and methods of compensation are presented. A model for the operation of the device in weak inversion is also proposed for exploitation of its physical primitives to make novel monolithic solutions. Functional implementations in various technologies is also detailed to allow future implementations chemical bionic circuits. Finally the ISFET integrate and fire neuron, which is the first of its kind, is presented to be used as a chemical based building block for many existing neuromorphic circuits. As an example of this a chemical imager is described for spatio-temporal monitoring of chemical species and an acid base discriminator for monitoring changes in concentration around a fixed threshold is also proposed