Symbolic framework for linear active circuits based on port equivalence using limit variables

Published versio

Power waves formulation of oscillation conditions: avoidance of bifurcation modes in cross-coupled VCO architectures

This paper discusses necessity of power-waves formulation to extend voltage-current oriented approaches based on linear concepts such as admittance/impedance operators and transfer-function representations. Importance of multi-physics methodologies, throughout power-waves formulation, for the analysis and design of crystal oscillators is discussed. Interpretation of bifurcation modes in differential cross-coupled VCO architectures in terms of gyrator-like behavior, is proposed. Impact of amplitude level control (ALC) on large-signal phase noise performances is underlined showing necessity of robust control analysis approach relative to power-energy considerations

Systematic Derivation for Quadrature Oscillators Using CCCCTAs

According to 16 nullor-mirror models of the current-controlled current conveyor transconductance amplifier (CCCCTA) and using nodal admittance matrix (NAM) expansion method, three different classes of the double-mode quadrature oscillators employed CCCCTAs and two grounded capacitors are synthesized. The class I oscillators have 32 different forms, the class II oscillators have 16 different forms, and the class III oscillators have four different forms. In all, 52 quadrature oscillators using CCCCTAs are obtained. Having used canonic number of components, the circuits are easy to be integrated and the condition for oscillation and the frequency of oscillation can be tuned by tuning bias currents of the CCCCTAs. The circuit analysis and simulation results have been included to support the generation method

On the Systematic Synthesis of OTA-Based KHN Filters

According to the nullor-mirror descriptions of OTA, the NAM expansion method for three different types of KHN filters employing OTAs is considered. The type-A filters employing five OTAs have 32 different forms, the type-B filters employing four OTAs have 32 different forms, and the type-C filters employing three OTAs have eight different forms. At last a total of 72 circuits are received. Having used canonic number of components, the circuits are easy to be integrated and both pole frequency and Q-factor can be tuned electronically through tuning bias currents of the OTAs. The MULTISIM simulation results have been included to verify the workability of the derived circuit

N-port rectangular-shaped distributed RC NETWORKS

Dielectric material between resistive thin film and pure conductor considered as n-port distributed RC networ

Novel Floating General Element Simulators Using CBTA

In this study, a novel floating frequency dependent negative resistor (FDNR), floating inductor, floating capacitor and floating resistor simulator circuit employing two CBTAs and three passive components is proposed. The presented circuit can realize floating FDNR, inductor, capacitor or resistor depending on the passive component selection. Since the passive elements are all grounded, this circuit is suitable for fully integrated circuit design. The circuit does not require any component matching conditions, and it has a good sensitivity performance with respect to tracking errors. Moreover, the proposed FDNR, inductance, capacitor and resistor simulator can be tuned electronically by changing the biasing current of the CBTA or can be controlled through the grounded resistor or capacitor. The high-order frequency dependent element simulator circuit is also presented. Depending on the passive component selection, it realizes high-order floating circuit defining as V(s) = snAI(s) or V(s) = s-nBI(s). The proposed floating FDNR simulator circuit and floating high-order frequency dependent element simulator circuit are demonstrated by using PSPICE simulation for 0.25 μm, level 7, TSMC CMOS technology parameters

A Novel (DDCC-SFG)-Based Systematic Design Technique of Active Filters

This paper proposes a novel idea for the synthesis of active filters that is based on the use of signal-flow graph (SFG) stamps of differential difference current conveyors (DDCCs). On the basis of an RLC passive network or a filter symbolic transfer function, an equivalent SFG is constructed. DDCCs’ SFGs are identified inside the constructed ‘active’ graph, and thus the equivalent circuit can be easily synthesized. We show that the DDCC and its ‘derivatives’, i.e. differential voltage current conveyors and the conventional current conveyors, are the main basic building blocks in such design. The practicability of the proposed technique is showcased via three application examples. Spice simulations are given to show the viability of the proposed technique

Robust H8 design for resonant control in a CVCF inverter application over load uncertainties

CVCF (constant voltage, constant frequency) inverters are electronic devices used to supply AC loads from DC storage elements such as batteries or photovoltaic cells. These devices are used to feed different kinds of loads; this uncertainty requires that the controller fulfills robust stability conditions while keeping required performance. To address this, a robust H8 design is proposed based on resonant control to track a pure sinusoidal voltage signal and to reject the most common harmonic signals in a wide range of loads. The design is based on the definition of performance bounds in error signal and weighting functions for covering most uncertainty ranges in loads. Experimentally, the H8 controller achieves high-quality output voltage signal with a total harmonic distortion less than 2%Peer ReviewedPostprint (published version

Evolutionary Synthesis of Analog Electronic Circuits Using EDA Algorithms

Disertační práce je zaměřena na návrh analogových elektronických obvodů pomocí algoritmů s pravěpodobnostními modely (algoritmy EDA). Prezentované metody jsou na základě požadovaných charakteristik cílových obvodů schopny navrhnout jak parametry použitých komponent tak také jejich topologii zapojení. Tři různé metody využití EDA algoritmů jsou navrženy a otestovány na příkladech skutečných problémů z oblasti analogových elektronických obvodů. První metoda je určena pro návrh pasivních analogových obvodů a využívá algoritmus UMDA pro návrh jak topologie zapojení tak také hodnot parametrů použitých komponent. Metoda je použita pro návrh admitanční sítě s požadovanou vstupní impedancí pro účely chaotického oscilátoru. Druhá metoda je také určena pro návrh pasivních analogových obvodů a využívá hybridní přístup - UMDA pro návrh topologie a metodu lokální optimalizace pro návrh parametrů komponent. Třetí metoda umožňuje návrh analogových obvodů obsahujících také tranzistory. Metoda využívá hybridní přístup - EDA algoritmus pro syntézu topologie a metoda lokální optimalizace pro určení parametrů použitých komponent. Informace o topologii je v jednotlivých jedincích populace vyjádřena pomocí grafů a hypergrafů.Dissertation thesis is focused on design of analog electronic circuits using Estimation of Distribution Algorithms (EDA). Based on the desired characteristics of the target circuits the proposed methods are able to design the parameters of the used components and theirs topology of connection as well. Three different methods employing EDA algorithms are proposed and verified on examples of real problems from the area of analog circuits design. The first method is capable to design passive analog circuits. The method employs UMDA algorithm which is used for determination of the parameters of the used components and synthesis of the topology of their connection as well. The method is verified on the problem of design of admittance network with desired input impedance function which is used as a part of chaotic oscillator circuit. The second method is also capable to design passive analog circuits. The method employs hybrid approach - UMDA for synthesis of the topology and local optimization method for determination of the parameters of the components. The third method is capable to design analog circuits which include also ac- tive components such as transistors. Hybrid approach is used. The topology is synthesized using EDA algorithm and the parameters are determined using a local optimization method. In the individuals of the population information about the topology is represented using graphs and hypergraphs.