3,697 research outputs found
Interpolation Methods for Binary and Multivalued Logical Quantum Gate Synthesis
A method for synthesizing quantum gates is presented based on interpolation
methods applied to operators in Hilbert space. Starting from the diagonal forms
of specific generating seed operators with non-degenerate eigenvalue spectrum
one obtains for arity-one a complete family of logical operators corresponding
to all the one-argument logical connectives. Scaling-up to n-arity gates is
obtained by using the Kronecker product and unitary transformations. The
quantum version of the Fourier transform of Boolean functions is presented and
a Reed-Muller decomposition for quantum logical gates is derived. The common
control gates can be easily obtained by considering the logical correspondence
between the control logic operator and the binary propositional logic operator.
A new polynomial and exponential formulation of the Toffoli gate is presented.
The method has parallels to quantum gate-T optimization methods using powers of
multilinear operator polynomials. The method is then applied naturally to
alphabets greater than two for multi-valued logical gates used for quantum
Fourier transform, min-max decision circuits and multivalued adders
Low Power Reversible Parallel Binary Adder/Subtractor
In recent years, Reversible Logic is becoming more and more prominent
technology having its applications in Low Power CMOS, Quantum Computing,
Nanotechnology, and Optical Computing. Reversibility plays an important role
when energy efficient computations are considered. In this paper, Reversible
eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design
III are proposed. In all the three design approaches, the full Adder and
Subtractors are realized in a single unit as compared to only full Subtractor
in the existing design. The performance analysis is verified using number
reversible gates, Garbage input/outputs and Quantum Cost. It is observed that
Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is
efficient compared to Design I, Design II and existing design.Comment: 12 pages,VLSICS Journa
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