Asynchronous performance analysis of a single-phase capacitor-start, capacitor-run permanent magnet motor

This work presents a detailed analysis of the asynchronous torque components (average cage, magnet braking torque and pulsating) for a single-phase capacitor-start, capacitor-run permanent magnet motor. The computed envelope of pulsating torque superimposed over the average electromagnetic torque leads to an accurate prediction of starting torque. The developed approach is realized by means of a combination of symmetrical components and d-q axes theory and it can be extended for any m-phase AC motor - induction, synchronous reluctance or synchronous permanent magnet. The resultant average electromagnetic torque is determined by superimposing the asynchronous torques and magnet braking torque effects

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

MHz rate and efficient synchronous heralding of single photons at telecom wavelengths

We report on the realization of a synchronous source of heralded single photons at telecom wavelengths with MHz heralding rates and high heralding efficiency. This source is based on the generation of photon pairs at 810 and 1550 nm via Spontaneous Parametric Down Conversion (SPDC) in a 1 cm periodically poled lithium niobate (PPLN) crystal pumped by a 532 nm pulsed laser. As high rates are fundamental for multi-photon experiments, we show that single telecom photons can be announced at 4.4MHz rate with 45% heralding efficiency. When we focus only on the optimization of the coupling of the heralded photon, the heralding efficiency can be increased up to 80%. Furthermore, we experimentally observe that group velocity mismatch inside long crystals pumped in a pulsed mode affects the spectrum of the emitted photons and their fibre coupling efficiency. The length of the crystal in this source has been chosen as a trade off between high brightness and high coupling efficiency.Comment: 10 pages, 2 figure

Asynchronous spiking neurons, the natural key to exploit temporal sparsity

Inference of Deep Neural Networks for stream signal (Video/Audio) processing in edge devices is still challenging. Unlike the most state of the art inference engines which are efficient for static signals, our brain is optimized for real-time dynamic signal processing. We believe one important feature of the brain (asynchronous state-full processing) is the key to its excellence in this domain. In this work, we show how asynchronous processing with state-full neurons allows exploitation of the existing sparsity in natural signals. This paper explains three different types of sparsity and proposes an inference algorithm which exploits all types of sparsities in the execution of already trained networks. Our experiments in three different applications (Handwritten digit recognition, Autonomous Steering and Hand-Gesture recognition) show that this model of inference reduces the number of required operations for sparse input data by a factor of one to two orders of magnitudes. Additionally, due to fully asynchronous processing this type of inference can be run on fully distributed and scalable neuromorphic hardware platforms

The Buffered \pi-Calculus: A Model for Concurrent Languages

Message-passing based concurrent languages are widely used in developing large distributed and coordination systems. This paper presents the buffered $\pi$-calculus --- a variant of the $\pi$-calculus where channel names are classified into buffered and unbuffered: communication along buffered channels is asynchronous, and remains synchronous along unbuffered channels. We show that the buffered $\pi$-calculus can be fully simulated in the polyadic $\pi$-calculus with respect to strong bisimulation. In contrast to the $\pi$-calculus which is hard to use in practice, the new language enables easy and clear modeling of practical concurrent languages. We encode two real-world concurrent languages in the buffered $\pi$-calculus: the (core) Go language and the (Core) Erlang. Both encodings are fully abstract with respect to weak bisimulations

Comparing the expressive power of the Synchronous and the Asynchronous pi-calculus

The Asynchronous pi-calculus, as recently proposed by Boudol and, independently, by Honda and Tokoro, is a subset of the pi-calculus which contains no explicit operators for choice and output-prefixing. The communication mechanism of this calculus, however, is powerful enough to simulate output-prefixing, as shown by Boudol, and input-guarded choice, as shown recently by Nestmann and Pierce. A natural question arises, then, whether or not it is possible to embed in it the full pi-calculus. We show that this is not possible, i.e. there does not exist any uniform, parallel-preserving, translation from the pi-calculus into the asynchronous pi-calculus, up to any ``reasonable'' notion of equivalence. This result is based on the incapablity of the asynchronous pi-calculus of breaking certain symmetries possibly present in the initial communication graph. By similar arguments, we prove a separation result between the pi-calculus and CCS.Comment: 10 pages. Proc. of the POPL'97 symposiu