4 research outputs found
Vesyla-II: An Algorithm Library Development Tool for Synchoros VLSI Design Style
High-level synthesis (HLS) has been researched for decades and is still
limited to fast FPGA prototyping and algorithmic RTL generation. A feasible
end-to-end system-level synthesis solution has never been rigorously proven.
Modularity and composability are the keys to enabling such a system-level
synthesis framework that bridges the huge gap between system-level
specification and physical level design. It implies that 1) modules in each
abstraction level should be physically composable without any irregular glue
logic involved and 2) the cost of each module in each abstraction level is
accurately predictable. The ultimate reasons that limit how far the
conventional HLS can go are precisely that it cannot generate modular designs
that are physically composable and cannot accurately predict the cost of its
design. In this paper, we propose Vesyla, not as yet another HLS tool, but as a
synthesis tool that positions itself in a promising end-to-end synthesis
framework and preserving its ability to generate physically composable modular
design and to accurately predict its cost metrics. We present in the paper how
Vesyla is constructed focusing on the novel platform it targets and the
internal data structures that highlights the uniqueness of Vesyla. We also show
how Vesyla will be positioned in the end-to-end synchoros synthesis framework
called SiLago