386 research outputs found
An Implementation of a Dual-Processor System on FPGA
In recent years, Field-Programmable Gate Arrays (FPGA) have evolved rapidly
paving the way for a whole new range of computing paradigms. On the other hand,
computer applications are evolving. There is a rising demand for a system that
is general-purpose and yet has the processing abilities to accommodate current
trends in application processing. This work proposes a design and
implementation of a tightly-coupled FPGA-based dual-processor platform. We
architect a platform that optimizes the utilization of FPGA resources and
allows for the investigation of practical implementation issues such as cache
design. The performance of the proposed prototype is then evaluated, as
different configurations of a uniprocessor and a dual-processor system are
studied and compared against each other and against published results for
common industry-standard CPU platforms. The proposed implementation utilizes
the Nios II 32-bit embedded soft-core processor architecture designed for the
Altera Cyclone III family of FPGAs
Cache Coherency for Symmetric Multiprocessor Systems on Programmable Chips
Rapid progress in the area of Field-Programmable Gate Arrays (FPGAs) has led to the availability of softcore processors that are simple to use, and can enable the development of a fully working system in minutes. This has lead to the enormous popularity of System-On-Programmable-Chip (SOPC) computing platforms. These softcore processors, while relatively simple compared to their leading-edge hardcore counterparts, are often designed with a number of advanced performance-enhancing features, such as instruction and data caches. Moreover, they are designed to be used in a uniprocessor or uncoupled multiprocessor architecture, and not in a tightly-coupled multiprocessing architecture. As a result, traditional cache-coherency protocols are not suitable for use with such systems. This thesis describes a system for enforcing cache coherency on symmetric multiprocessing (SMP) systems using softcore processors. A hybrid protocol that incorporates hardware and software to enforce cache coherency is presented
A TrustZone-assisted secure silicon on a co-design framework
Dissertação de mestrado em Engenharia Eletrónica Industrial e ComputadoresEmbedded systems were for a long time, single-purpose and closed systems, characterized
by hardware resource constraints and real-time requirements. Nowadays, their functionality is
ever-growing, coupled with an increasing complexity and heterogeneity. Embedded applications
increasingly demand employment of general-purpose operating systems (GPOSs) to handle operator
interfaces and general-purpose computing tasks, while simultaneously ensuring the strict
timing requirements. Virtualization, which enables multiple operating systems (OSs) to run on
top of the same hardware platform, is gaining momentum in the embedded systems arena,
driven by the growing interest in consolidating and isolating multiple and heterogeneous environments.
The penalties incurred by classic virtualization approaches is pushing research towards
hardware-assisted solutions. Among the existing commercial off-the-shelf (COTS) technologies for
virtualization, ARM TrustZone technology is gaining momentum due to the supremacy and lower
cost of TrustZone-enabled processors.
Programmable system-on-chips (SoCs) are becoming leading players in the embedded systems
space, because the combination of a plethora of hard resources with programmable logic
enables the efficient implementation of systems that perfectly fit the heterogeneous nature of
embedded applications. Moreover, novel disruptive approaches make use of field-programmable
gate array (FPGA) technology to enhance virtualization mechanisms.
This master’s thesis proposes a hardware-software co-design framework for easing the economy
of addressing the new generation of embedded systems requirements. ARM TrustZone is
exploited to implement the root-of-trust of a virtualization-based architecture that allows the execution
of a GPOS side-by-side with a real-time OS (RTOS). RTOS services were offloaded to hardware,
so that it could present simultaneous improvements on performance and determinism. Instead
of focusing in a concrete application, the goal is to provide a complete framework, specifically tailored
for Zynq-base devices, that developers can use to accelerate a bunch of distinct applications
across different embedded industries.Os sistemas embebidos foram, durante muitos anos, sistemas com um simples e único
propósito, caracterizados por recursos de hardware limitados e com cariz de tempo real. Hoje
em dia, o número de funcionalidades começa a escalar, assim como o grau de complexidade
e heterogeneidade. As aplicações embebidas exigem cada vez mais o uso de sistemas operativos
(OSs) de uso geral (GPOS) para lidar com interfaces gráficas e tarefas de computação de
propósito geral. Porém, os seus requisitos primordiais de tempo real mantém-se. A virtualização
permite que vários sistemas operativos sejam executados na mesma plataforma de hardware.
Impulsionada pelo crescente interesse em consolidar e isolar ambientes múltiplos e heterogéneos,
a virtualização tem ganho uma crescente relevância no domínio dos sistemas embebidos.
As adversidades que advém das abordagens de virtualização clássicas estão a direcionar estudos
no âmbito de soluções assistidas por hardware. Entre as tecnologias comerciais existentes, a
tecnologia ARM TrustZone está a ganhar muita relevância devido à supremacia e ao menor custo
dos processadores que suportam esta tecnologia.
Plataformas hibridas, que combinam processadores com lógica programável, estão em crescente
penetração no domínio dos sistemas embebidos pois, disponibilizam um enorme conjunto
de recursos que se adequam perfeitamente à natureza heterogénea dos sistemas atuais. Além
disso, existem soluções recentes que fazem uso da tecnologia de FPGA para melhorar os mecanismos
de virtualização.
Esta dissertação propõe uma framework baseada em hardware-software de modo a cumprir
os requisitos da nova geração de sistemas embebidos. A tecnologia TrustZone é explorada para
implementar uma arquitetura que permite a execução de um GPOS lado-a-lado com um sistemas
operativo de tempo real (RTOS). Os serviços disponibilizados pelo RTOS são migrados
para hardware, para melhorar o desempenho e determinismo do OS. Em vez de focar numa
aplicação concreta, o objetivo é fornecer uma framework especificamente adaptada para dispositivos
baseados em System-on-chips Zynq, de forma a que developers possam usar para acelerar
um vasto número de aplicações distintas em diferentes setores
Multiprocessor platform using LEON3 processor
The recent advances in embedded systems world, lead us to more complex systems with
application specific blocks (IP cores), the System on Chip (SoC) devices. A good example
of these complex devices can be encountered in the cell phones that can have image processing
cores, communication cores, memory card cores, and others.
The need of augmenting systems’ processing performance with lowest power, leads to a
concept of Multiprocessor System on Chip (MSoC) in which the execution of multiple
tasks can be distributed along various processors.
This thesis intends to address the creation of a synthesizable multiprocessing system to be
placed in a FPGA device, providing a good flexibility to tailor the system to a specific application.
To deliver a multiprocessing system, will be used the synthesisable 32-bit
SPARC V8 compliant, LEON3 processor.Os avanços recentes no mundo dos sistemas embebidos levam-nos a sistemas mais
complexos com blocos para aplicações específicas (IP cores), os dispositivos System on
Chip (SoC). Um bom exemplo destes complexos dispositivos pode ser encontrado nos
telemóveis, que podem conter cores de processamento de imagem, cores de comunicações,
cores para cartões de memória, entre outros.
A necessidade de aumentar o desempenho dos sistemas de processamento com o menor
consumo possível, leva ao conceito de Multiprocessor System on Chip (MSoC) em que a
execução de múltiplas tarefas pode ser distribuída por vários processadores.
Esta Tese pretende abordar a criação de um sistema de multiprocessamento sintetizável
para ser colocado numa FPGA, proporcionando uma boa flexibilidade para a adaptação do
sistema a uma aplicação específica. Para obter o sistema multiprocessamento, irá ser
utilizado o processador sintetizável SPARC V8 de 32-bit, LEON3
Multiprocessing techniques for unmanned multifunctional satellites Final report,
Simulation of on-board multiprocessor for long lived unmanned space satellite contro
A real-time asymmetric multiprocessor-reconfigurable system-on-chip architecture
We propose an asymmetric multi-processor SoC architecture, featuring a master CPU running uClinux, and multiple loosely-coupled slave CPUs running real-time threads assigned by the master CPU. Real-time SoC architectures often demand a compromise between a generic platform for different applications, and application-specific customizations to achieve performance requirements. Our proposed architecture offers a generic platform running a conventional embedded operating system providing a traditional software-oriented development approach, while multiple slave CPUs act as a dedicated independent real-time threads execution unit running in parallel of master CPU to achieve performance requirements. In this paper, the architecture is described, including the application / threading development environment. The performance of the architecture with several standard benchmark routines is also analysed
Digital signal processor fundamentals and system design
Digital Signal Processors (DSPs) have been used in accelerator systems for more than fifteen years and have largely contributed to the evolution towards digital technology of many accelerator systems, such as machine protection, diagnostics and control of beams, power supply and motors. This paper aims at familiarising the reader with DSP fundamentals, namely DSP characteristics and processing development. Several DSP examples are given, in particular on Texas Instruments DSPs, as they are used in the DSP laboratory companion of the lectures this paper is based upon. The typical system design flow is described; common difficulties, problems and choices faced by DSP developers are outlined; and hints are given on the best solution
Characterisation of a reconfigurable free space optical interconnect system for parallel computing applications and experimental validation using rapid prototyping technology
Free-space optical interconnects (FSOIs) are widely seen as a potential solution to
present and future bandwidth bottlenecks for parallel processing applications.
This thesis will be focused on the study of a particular FSOI system called Optical
Highway (OH). The OH is a polarised beam routing system which uses Polarising
Beam Splitters and Liquid Crystals (PBS/LC) assemblies to perform reconfigurable
interconnection networks. The properties of the OH make it suitable for implementing
different passive static networks.
A technology known as Rapid Prototyping (RP) will be employed for the first time in
order to create optomechanical structures at low cost and low production times. Off-theshelf
optical components will also be characterised in order to implement the OH.
Additionally, properties such as reconfigurability, scalability, tolerance to misalignment
and polarisation losses will be analysed. The OH will be modelled at three levels: node,
optical stage and architecture. Different designs will be proposed and a particular
architecture, Optimised Cut-Through Ring (OCTR), will be experimentally
implemented. Finally, based on this architecture, a new set of properties will be defined
in order to optimise the efficiency of the optical channels
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Task Partitioning and Mapping Algorithms for Multi-core Packet Processing Systems
In this work, we have explored different task mapping algorithms for multi-core, packet processing systems. we also implemented these algorithms and compared the results of the algorithms. We first reviewed the previously designed algorithms which include UDFS algorithm and duplication process. We then applied the KL algorithm to our problem and were able to reduce the inter-processor communication by 20% while maintaining the similar utilization. We then modified the original KL algorithm by considering utilization during the mapping process. In this extended KL algorithm, we incorporated a tradeoff factor alpha to tradeoff between inter-processor communication and processor utilization. The best alpha is different for different system configurations in terms of communication bandwidth and computing power. Simulated annealing(SA) algorithm was then implemented. The parameters for SA algorithm were decided by following literature or by doing experiments. Results from SA algorithm shows that it can produce decent results that are comparable to KL algorithm. In order to further improve the utilization, merging operation was applied to the task graph before mapping algorithms were applied. The mapping results showed that merging is a good way to improve the utilization and at the same time keep the communication cost lower. Finally, we applied the mapping algorithms to different packet processing system architectures. The results show how inter-processor communication cost and processor utilization change as system architecture changes
FPGA Based Embedded Multiprocessor Architecture
Multiprocessor is a typical subject within the Computer architecture field of scope. A new methodology based on practical sessions with real devices and design is proposed. Embedded multiprocessor design presents challenges and opportunities that stem from task coarse granularity and the large number of inputs and outputs for each task. We have therefore designed a new architecture called embedded concurrent computing (ECC), which is implementing on FPGA chip using VHDL. The design methodology is expected to allow scalable embedded multiprocessors for system expansion. In recent decades, two forces have driven the increase of the processor performance: Advances in very large-scale integration (VLSI) technology and Micro architectural enhancements. Therefore, we aim to design the full architecture of an embedded processor for realistic to perform arithmetic, logical, shifting and branching operations. We will be synthesize and evaluated the embedded system based on Xilinx environment. Processor performance is going to be improving through clock speed increases and the clock speed increases and the exploitation of instruction- level parallelism. We will be designing embedded multiprocessor based on Xilinx environment or Modelsim environment
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