Medical microprocessor systems

The practical classes and laboratory work in the discipline "Medical microprocessor systems", performed using software in the programming environment of microprocessors Texas Instruments (Code Composer Studio) and using of digital microprocessors of the Texas Instruments DSK6400 family, and models of electrical equipment in the environment of graphical programming LabVIEW 2010.Лабораторний практикум з програмування та побудови медичних мікропроцесорних систем, який викладено у навчальному посібнику допомагає накопичувати й ефективно використовувати отриману інформацію з теоретичного курсу на всіх стадіях навчального процесу, що є важливим для підготовки магістрів та необхідною ланкою у науковому пізнанні практичних основ біомедичної електроніки.The laboratory workshop on the programming and construction of medical microprocessor systems, which is outlined in the tutorial, helps to accumulate and effectively use the information obtained from a theoretical course at all stages of the educational process, which is important for the preparation of masters and a necessary link in the scientific knowledge of the practical basics of biomedicine.Лабораторный практикум по программированию и построению медицинских микропроцессорных систем, который изложен в учебном пособии помогает накапливать и эффективно использовать полученную информацию из теоретического курса на всех стадиях учебного процесса, что важно для подготовки магистров и является необходимым звеном в научном познании практических основ биомедицинской электроники

Design and implementation of an array language for computational science on a heterogeneous multicore architecture

The packing of multiple processor cores onto a single chip has become a mainstream solution to fundamental physical issues relating to the microscopic scales employed in the manufacture of semiconductor components. Multicore architectures provide lower clock speeds per core, while aggregate floating-point capability continues to increase. Heterogeneous multicore chips, such as the Cell Broadband Engine (CBE) and modern graphics chips, also address the related issue of an increasing mismatch between high processor speeds, and huge latency to main memory. Such chips tackle this memory wall by the provision of addressable caches; increased bandwidth to main memory; and fast thread context switching. An associated cost is often reduced functionality of the individual accelerator cores; and the increased complexity involved in their programming. This dissertation investigates the application of a programming language supporting the first-class use of arrays; and capable of automatically parallelising array expressions; to the heterogeneous multicore domain of the CBE, as found in the Sony PlayStation 3 (PS3). The language is a pre-existing and well-documented proper subset of Fortran, known as the ‘F’ programming language. A bespoke compiler, referred to as E , is developed to support this aim, and written in the Haskell programming language. The output of the compiler is in an extended C++ dialect known as Offload C++, which targets the PS3. A significant feature of this language is its use of multiple, statically typed, address spaces. By focusing on generic, polymorphic interfaces for both the generated and hand constructed code, a number of interesting design patterns relating to the memory locality are introduced. A suite of medium-sized (100-700 lines), real-world benchmark programs are used to evaluate the performance, correctness, and scalability of the compiler technology. Absolute speedup values, well in excess of one, are observed for all of the programs. The work ultimately demonstrates that an array language can significantly reduce the effort expended to utilise a parallel heterogeneous multicore architecture, while retaining high performance. A substantial, related advantage in using standard ‘F’ is that any Fortran compiler can create debuggable, and competitively performing serial programs

A new parallelisation technique for heterogeneous CPUs

Parallelization has moved in recent years into the mainstream compilers, and the demand for parallelizing tools that can do a better job of automatic parallelization is higher than ever. During the last decade considerable attention has been focused on developing programming tools that support both explicit and implicit parallelism to keep up with the power of the new multiple core technology. Yet the success to develop automatic parallelising compilers has been limited mainly due to the complexity of the analytic process required to exploit available parallelism and manage other parallelisation measures such as data partitioning, alignment and synchronization. This dissertation investigates developing a programming tool that automatically parallelises large data structures on a heterogeneous architecture and whether a high-level programming language compiler can use this tool to exploit implicit parallelism and make use of the performance potential of the modern multicore technology. The work involved the development of a fully automatic parallelisation tool, called VSM, that completely hides the underlying details of general purpose heterogeneous architectures. The VSM implementation provides direct and simple access for users to parallelise array operations on the Cell’s accelerators without the need for any annotations or process directives. This work also involved the extension of the Glasgow Vector Pascal compiler to work with the VSM implementation as a one compiler system. The developed compiler system, which is called VP-Cell, takes a single source code and parallelises array expressions automatically. Several experiments were conducted using Vector Pascal benchmarks to show the validity of the VSM approach. The VP-Cell system achieved significant runtime performance on one accelerator as compared to the master processor’s performance and near-linear speedups over code runs on the Cell’s accelerators. Though VSM was mainly designed for developing parallelising compilers it also showed a considerable performance by running C code over the Cell’s accelerators

Ein Modell zur effizienten Parallelisierung von Algorithmen auf komplexen, dynamischen Datenstrukturen

Moderne berechnungsintensive Algorithmen, beispielsweise adaptive numerische Lösungsverfahren für partielle Differentialgleichungen, arbeiten oftmals auf komplexen, dynamischen Datenstrukturen. Die Implementierung solcher Algorithmen auf Parallelrechnern mit verteiltem Speicher mittels Datenpartitionierung wirft zahlreiche Probleme auf (z.B. Lastverteilung). Im Rahmen der vorliegenden Arbeit wurde das neue parallele Programmiermodell Dynamic Distributed Data (DDD) entwickelt, durch das die Parallelisierungsarbeit vom Design der verteilten Datenstrukturen bis hin zur Erstellung des portablen, parallelen und effizienten Programmcodes unterstützt wird. Dem DDD-Konzept liegt ein graphbasiertes formales Modell zugrunde. Dabei wird die Datenstruktur des jeweiligen Programms (z.B. unstrukturierte Gitter) formal auf einen verteilten Graphen abgebildet, der aus mehreren lokalen Graphen besteht. Das formale Modell dient als Spezifikation des Programmiermodells und gleichzeitig zur Definition der wichtigen in dieser Arbeit verwendeten Begriffe. Der Systemarchitektur von DDD-basierten Anwendungen liegt ein Schichtenmodell zugrunde, den Kern stellt dabei die DDD-Programmbibliothek dar. Diese bietet Funktionen zur dynamischen Definition verteilter Datentypen und zur Verwaltung lokaler Objekte. In den Überlappungsbereichen der lokalen Graphen stehen abstrakte Kommunikationsfunktionen in Form von sog. Interfaces zur Verfügung. Die wesentliche Neuerung gegenüber nahezu allen bestehenden Arbeiten ist jedoch die Möglichkeit zur dynamischen Veränderung des verteilten Graphen; dies ermöglicht es beispielsweise, dynamische Lastverteilung oder Gittergenerierungsverfahren einfach und effizient zu implementieren. Damit können beliebig komplexe Datentopologien dynamisch erzeugt, migriert und wieder entfernt werden