139 research outputs found
Modeling and Energy Optimization of LDPC Decoder Circuits with Timing Violations
This paper proposes a "quasi-synchronous" design approach for signal
processing circuits, in which timing violations are permitted, but without the
need for a hardware compensation mechanism. The case of a low-density
parity-check (LDPC) decoder is studied, and a method for accurately modeling
the effect of timing violations at a high level of abstraction is presented.
The error-correction performance of code ensembles is then evaluated using
density evolution while taking into account the effect of timing faults.
Following this, several quasi-synchronous LDPC decoder circuits based on the
offset min-sum algorithm are optimized, providing a 23%-40% reduction in energy
consumption or energy-delay product, while achieving the same performance and
occupying the same area as conventional synchronous circuits.Comment: To appear in IEEE Transactions on Communication
VLSI implementation of a multi-mode turbo/LDPC decoder architecture
Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel contributions of this paper are: i) tackling the reconfiguration issue introducing a formal and systematic treatment that, to the best of our knowledge, was not previously addressed; ii) proposing a reconfigurable NoCbased turbo/LDPC decoder architecture and showing that wide flexibility can be achieved with a small complexity overhead. Obtained results show that dynamic switching between most of considered communication standards is possible without pausing the decoding activity. Moreover, post-layout results show that tailoring the proposed architecture to the WiMAX standard leads to an area occupation of 2.75 mm2 and a power consumption of 101.5 mW in the worst case
Low-Power 400-Gbps Soft-Decision LDPC FEC for Optical Transport Networks
We present forward error correction systems based on soft-decision low-density parity check (LDPC) codes for applications in 100â400-Gbps optical transport networks. These systems are based on the low-complexity âadaptive degenerationâ decoding algorithm, which we introduce in this paper, along with randomly-structured LDPC codes with block lengths from 30 000 to 60 000 bits and overhead (OH) from 6.7% to 33%. We also construct a 3600-bit prototype LDPC code with 20% overhead, and experimentally show that it has no error floor above a bit error rate (BER) of 10â15 using a field-programmable gate array (FPGA)-based hardware emulator. The projected net coding gain at a BER of 10â15 ranges from 9.6 dB at 6.7% OH to 11.2 dB at 33% OH. We also present application-specific integrated circuit synthesis results for these decoders in 28 nm fully depleted silicon on insulator technology, which show that they are capable of 400-Gbps operation with energy consumption of under 3 pJ per information bit
Scalable and Low Power LDPC Decoder Design Using High Level Algorithmic Synthesis
This paper presents a scalable and low power low-density parity-check (LDPC) decoder design for the next generation wireless handset SoC. The methodology is based on high level synthesis: PICO (program-in chip-out) tool was used to produce efficient RTL directly from a sequential untimed C algorithm. We propose two parallel LDPC decoder architectures: (1) per-layer decoding architecture with scalable parallelism, and (2) multi-layer pipelined decoding architecture to achieve higher throughput. Based on the PICO technology, we have implemented a two-layer pipelined decoder on a TSMC 65nm 0.9V 8-metal layer CMOS technology with a core area of 1.2 mm2. The maximum achievable throughput is 415 Mbps when operating at 400 MHz clock frequency and the estimated peak power consumption is 180 mW.NokiaNokia Siemens Networks (NSN)XilinxNational Science Foundatio
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Low-complexity high-speed VLSI design of low-density parity-check decoders
Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g., N>1000 bits), which lead to a linear increase of the size of memory for storing all the soft messages in LDPC decoding. In the next generation communication systems, the target data rates range from a few hundred Mbit/sec to several Gbit/sec. To achieve those very high decoding throughput, a large amount of computation units are required, which will significantly increase the hardware cost and power consumption of LDPC decoders. LDPC codes are decoded using iterative decoding algorithms. The decoding latency and power consumption are linearly proportional to the number of decoding iterations. A decoding approach with fast convergence speed is highly desired in practice.
This thesis considers various VLSI design issues of LDPC decoder and develops efficient approaches for reducing memory requirement, low complexity implementation, and high speed decoding of LDPC codes. We propose a memory efficient partially parallel decoder architecture suited for quasi-cyclic LDPC (QC-LDPC) codes using Min-Sum decoding algorithm. We develop an efficient architecture for general permutation matrix based LDPC codes. We have explored various approaches to linearly increase the decoding throughput with a small amount of hardware overhead. We develop a multi-Gbit/sec LDPC decoder architecture for QC-LDPC codes and prototype an enhanced partially parallel decoder architecture for a Euclidian geometry based LDPC code on FPGA. We propose an early stopping scheme and an extended layered decoding method to reduce the number of decoding iterations for undecodable and decodable sequence received from channel. We also propose a low-complexity optimized 2-bit decoding approach which requires comparable implementation complexity to weighted bit flipping based algorithms but has much better decoding performance and faster convergence speed
A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS
We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and is runtime-programmable to process different code matrices (including all rates and block lengths specified by IEEE 802.11n). The register-transfer-level implementation has been optimized for best energy efficiency. The corresponding 90nm CMOS ASIC has a core area of 1.77mm2 and achieves a maximum throughput of 680 Mbps at 346MHz clock frequency and 10 decoding iterations. The measured energy efficiency is 15.8 pJ/bit/iteration at a nominal operating voltage of 1.0V
Unified turbo/LDPC code decoder architecture for deep-space communications
Deep-space communications are characterized by extremely
critical conditions; current standards foresee the usage of both turbo
and low-density-parity-check (LDPC) codes to ensure recovery from
received errors, but each of them displays consistent drawbacks.
Code concatenation is widely used in all kinds of communication to
boost the error correction capabilities of single codes; serial
concatenation of turbo and LDPC codes has been recently proven
effective enough for deep space communications, being able to
overcome the shortcomings of both code types. This work extends
the performance analysis of this scheme and proposes a novel
hardware decoder architecture for concatenated turbo and LDPC
codes based on the same decoding algorithm. This choice leads to a
high degree of datapath and memory sharing; postlayout
implementation results obtained with complementary metal-oxide
semiconductor (CMOS) 90 nm technology show small area
occupation (0.98 mm
2
) and very low power consumption (2.1 mW)
Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling
This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading
channels and general AWGN channels. A model of a memory-efficient low-power
high-throughput multi-rate array LDPC decoder as well as its FPGA implementa-
tion results is first presented. Then, I propose a decoding scheme that provides the
feature of constant-time decoding and thus facilitates real-time applications where
guaranteed data rate is required. It pre-analyzes each received data frame to estimate the maximum number of necessary iterations for frame convergence. The
results are then used to dynamically adjust decoder frequency and switch between
multiple-voltage levels; thereby energy use is minimized. This is in contrast to the
conventional fixed-iteration decoding schemes that operate at a fixed voltage level
regardless of the quality of data received. Analysis shows that the proposed decoding
scheme is widely applicable for both two-phase message-passing (TPMP) decoding
algorithm and turbo decoding message passing (TDMP) decoding algorithm in block
fading channels, and it is independent of the specific LDPC decoder architecture. A
decoder architecture utilizing our recently published multi-rate decoding architecture
for general AWGN channels is also presented. The result of this thesis is a decoder
design scheme that provides a judicious trade-off between power consumption and
coding gain
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