1,481 research outputs found
Algorithms for Power Aware Testing of Nanometer Digital ICs
At-speed testing of deep-submicron digital very large scale integrated (VLSI) circuits
has become mandatory to catch small delay defects. Now, due to continuous shrinking
of complementary metal oxide semiconductor (CMOS) transistor feature size, power
density grows geometrically with technology scaling. Additionally, power dissipation
inside a digital circuit during the testing phase (for test vectors under all fault models
(Potluri, 2015)) is several times higher than its power dissipation during the normal
functional phase of operation. Due to this, the currents that flow in the power grid during
the testing phase, are much higher than what the power grid is designed for (the
functional phase of operation). As a result, during at-speed testing, the supply grid
experiences unacceptable supply IR-drop, ultimately leading to delay failures during
at-speed testing. Since these failures are specific to testing and do not occur during
functional phase of operation of the chip, these failures are usually referred to false
failures, and they reduce the yield of the chip, which is undesirable.
In nanometer regime, process parameter variations has become a major problem.
Due to the variation in signalling delays caused by these variations, it is important to
perform at-speed testing even for stuck faults, to reduce the test escapes (McCluskey
and Tseng, 2000; Vorisek et al., 2004). In this context, the problem of excessive peak
power dissipation causing false failures, that was addressed previously in the context of
at-speed transition fault testing (Saxena et al., 2003; Devanathan et al., 2007a,b,c), also
becomes prominent in the context of at-speed testing of stuck faults (Maxwell et al.,
1996; McCluskey and Tseng, 2000; Vorisek et al., 2004; Prabhu and Abraham, 2012;
Potluri, 2015; Potluri et al., 2015). It is well known that excessive supply IR-drop during
at-speed testing can be kept under control by minimizing switching activity during
testing (Saxena et al., 2003). There is a rich collection of techniques proposed in the past
for reduction of peak switching activity during at-speed testing of transition/delay faults
ii
in both combinational and sequential circuits. As far as at-speed testing of stuck faults
are concerned, while there were some techniques proposed in the past for combinational
circuits (Girard et al., 1998; Dabholkar et al., 1998), there are no techniques concerning
the same for sequential circuits. This thesis addresses this open problem. We
propose algorithms for minimization of peak switching activity during at-speed testing
of stuck faults in sequential digital circuits under the combinational state preservation
scan (CSP-scan) architecture (Potluri, 2015; Potluri et al., 2015). First, we show that,
under this CSP-scan architecture, when the test set is completely specified, the peak
switching activity during testing can be minimized by solving the Bottleneck Traveling
Salesman Problem (BTSP). This mapping of peak test switching activity minimization
problem to BTSP is novel, and proposed for the first time in the literature.
Usually, as circuit size increases, the percentage of don’t cares in the test set increases.
As a result, test vector ordering for any arbitrary filling of don’t care bits
is insufficient for producing effective reduction in switching activity during testing of
large circuits. Since don’t cares dominate the test sets for larger circuits, don’t care
filling plays a crucial role in reducing switching activity during testing. Taking this
into consideration, we propose an algorithm, XStat, which is capable of performing test
vector ordering while preserving don’t care bits in the test vectors, following which, the
don’t cares are filled in an intelligent fashion for minimizing input switching activity,
which effectively minimizes switching activity inside the circuit (Girard et al., 1998).
Through empirical validation on benchmark circuits, we show that XStat minimizes
peak switching activity significantly, during testing.
Although XStat is a very powerful heuristic for minimizing peak input-switchingactivity,
it will not guarantee optimality. To address this issue, we propose an algorithm
that uses Dynamic Programming to calculate the lower bound for a given sequence
of test vectors, and subsequently uses a greedy strategy for filling don’t cares in this
sequence to achieve this lower bound, thereby guaranteeing optimality. This algorithm,
which we refer to as DP-fill in this thesis, provides the globally optimal solution for
minimizing peak input-switching-activity and also is the best known in the literature
for minimizing peak input-switching-activity during testing. The proof of optimality of
DP-fill in minimizing peak input-switching-activity is also provided in this thesis
An FSM Re-Engineering Approach to Sequential Circuit Synthesis by State Splitting
We propose Finite State Machine (FSM) re-engineering, a
performance enhancement framework for FSM synthesis and
optimization. It starts with the traditional FSM synthesis procedure,
then proceeds to re-construct a functionally equivalent
but topologically different FSM based on the optimization
objective, and concludes with another round of FSM synthesis
on the re-constructed FSM. This approach explores a larger
solution space that consists of a set of FSMs functionally
equivalent to the original one, making it possible to obtain
better solutions than in the original FSM. Guided by the result
from the #2;rst round of synthesis, the solution space exploration
process can be rapid and cost-ef#2;cient.
We apply this framework to FSM state encoding for power
minimization and area minimization. The FSM is #2;rst minimized
and encoded using existing state encoding algorithms.
Then we develop both a heuristic algorithm and a genetic
algorithm to re-construct the FSM. Finally, the FSM is reencoded
by the same encoding algorithms. To demonstrate
the effectiveness of this framework, we conduct experiments
on MCNC91 sequential circuit benchmarks. The circuits are
read in and synthesized in SIS environment. After FSM
re-engineering are performed, we measure the power, area
and delay in the newly synthesized circuits. In the powerdriven
synthesis, we observe an average 5.5% of total power
reduction with 1.3% area increase and 1.3% delay increase.
This results are in general better than other low power state
encoding techniques on comparable cases. In the area-driven
synthesis, we observe an average 2.7% area reduction, 1.8%
delay reduction, and 0.4% power increase. Finally, we use
integer linear programming to obtain the optimal low power
state encoding for benchmarks of small size. We #2;nd that the
optimal solutions in the re- engineered FSMs are 1% to 8%
better than the optimal solutions in the original FSMs in terms
of power minimization
Redundant Logic Insertion and Fault Tolerance Improvement in Combinational Circuits
This paper presents a novel method to identify and insert redundant logic
into a combinational circuit to improve its fault tolerance without having to
replicate the entire circuit as is the case with conventional redundancy
techniques. In this context, it is discussed how to estimate the fault masking
capability of a combinational circuit using the truth-cum-fault enumeration
table, and then it is shown how to identify the logic that can introduced to
add redundancy into the original circuit without affecting its native
functionality and with the aim of improving its fault tolerance though this
would involve some trade-off in the design metrics. However, care should be
taken while introducing redundant logic since redundant logic insertion may
give rise to new internal nodes and faults on those may impact the fault
tolerance of the resulting circuit. The combinational circuit that is
considered and its redundant counterparts are all implemented in semi-custom
design style using a 32/28nm CMOS digital cell library and their respective
design metrics and fault tolerances are compared
A survey of scan-capture power reduction techniques
With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing
Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor
During device testing, one of the aspects to be considered is the minimization of the switching activity of the circuit under test in order to steer clear of introducing problems due to device overheating. Nevertheless, there are also certain scenarios during which the maximization of switching activity of the circuit under test (CUT) or of certain parts of it could be proven beneficial e.g., during Burn-In (BI), where internal stress is often produced by applying suitable stimuli. This can be done in a functional manner based on Software-based Self-Test in order to avoid possible damages to the CUT and/or any kind of yield loss. However, the generation of suitable test programs for this task represents a non-trivial task. In this paper we consider a scenario where the circuitry to be stressed is a pipelined processor. We present a methodology, based on formal techniques, able to automatically generate the best functional stress stimuli, i.e., a short and repeatable sequence of assembly instructions, which is guaranteed to induce the maximum switching activity within a given target processor module over a pre-defined time period. For the purposes of our experiments we used the OpenRISC 1200. The gathered experimental results demonstrate the effectiveness of the developed method. In particular, we show that the time for generating the best instruction sequence is limited in most cases, while the generated sequence can always achieve a significantly higher sustained toggling activity than any other solution
Low-Capture-Power Test Generation for Scan-Based At-Speed Testing
Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR drop caused by high power dissipation when a test response is captured. This paper addresses this critical problem with a novel low-capture-power X-filling method of assigning 0\u27s and 1\u27s to unspecified (X) bits in a test cube obtained during ATPG. This method reduces the circuit switching activity in capture mode and can be easily incorporated into any test generation flow to achieve capture power reduction without any area, timing, or fault coverage impact. Test vectors generated with this practical method greatly improve the applicability of scan-based at-speed testing by reducing the risk of test yield lossIEEE International Conference on Test, 2005, 8 November 2005, Austin, TX, US
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