An 8-Bit Analog-to-Digital Converter for Battery Operated Wireless Sensor Nodes

Wireless sensing networks (WSNs) collect analog information transduced into the form of a voltage or current. This data is typically converted into a digital representation of the value and transmitted wirelessly using various modulation techniques. As the available power and size is limited for wireless sensor nodes in many applications, a medium resolution Analog-to-Digital Converter (ADC) is proposed to convert a sensed voltage with moderate speeds to lower power consumption. Specifications also include a rail-to-rail input range and minimized errors associated with offset, gain, differential nonlinearity, and integral nonlinearity. To achieve these specifications, an 8-bit successive approximation register ADC is developed which has a conversion time of nine clock cycles. This ADC features a charge scaling array included to achieve minimized power consumption and area by reducing unit capacitance in the digital-to-analog converter. Furthermore, a latched comparator provides fast decisions utilizing positive feedback. The ADC was designed and simulated using Cadence Virtuoso with parasitic extraction over expected operating temperature range of 0 – 85°C. The design was fabricated using TSMC’s 65 nanometer RF GP process and tested on a printed circuit board to verify design specifications. The measured results for the device show an offset and gain error of +7 LSB and 31.1 LSB, respectively, and a DNL range of -0.9 LSB to +0.8 LSB and an INL range of approximately -4.6 LSB to +12 LSB. The INL is much improved in regard to the application of the temperature sensor. The INL for this region of interest is from -3.5 LSB to +2.8 LSB

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

A 0.35 μm CMOS 17-bit@40-kS/s cascade 2-1 ΣΔ modulator with programmable gain and programmable chopper stabilization

This paper describes a 0.35μm CMOS chopper-stabilized Switched-Capacitor 2-1 cascade ΣDelta; modulator for automotive sensor interfaces. For a better fitting to the characteristics of different sensor outputs, the modulator includes a programmable set of gains (x0.5, x1, x2, and x4) and a programmable set of chopper frequencies (fs/16, fs/8, fs/4 and fs/2). It has also been designed to operate within the restrictive environmental conditions of automotive electronics (-40°C, 175°C). The modulator architecture has been selected after an exhaustive comparison among multiple ΣΔM topologies in terms of resolution, speed and power dissipation. The design of the modulator building blocks is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12MHz and consumes, all together, 14.7mW from a single 3.3-V supply. Experimental measurements result in 99.77dB of Dynamic Range (DR), which combined with the gain programmability leads to an overall DR of 112dB. This puts the presented design beyond the state-of-the-art according with the existing bibliography

High performance amplifier topologies implemented with a micro-machined vibrating capacitor

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (leaves 201-206).In this work, the design of a MEMS based differential amplifier is investigated. The goal of this investigation is to design, fabricate and characterize a differential amplifier whose performance is based on a physically coupled, but electrically isolated fully differential mechanical transconductor input stage that is fabricated using SOI-MEMS technology. The MEMS sensor will act as a vibrating capacitor input stage. It will provide galvanic isolation and up-modulation of the input signal as it vibrates. The galvanic isolation facilitates low-leakage inputs and a very wide input common mode voltage range. The up-modulation provides a means for achieving a low input referred offset voltage and low-noise via the use of correlated double sampling or chopper stabilization. At the system level, this amplifier consists of two major loops: the drive loop and a sense loop. The drive loop includes half of the MEMS structure along with some electronics and provides a means of moving the beam at a constant frequency. The drive loop's design was facilitated by describing function analysis. The drive loop vibrated the beam at its mechanical resonance because at that frequency, the displacement of the beam is maximized for a given electrostatic force and consequently, the sensitivity of the amplifier is maximized. The sense loop includes the other half of the beam and some electronics whose role is to process the differential input signal applied at the MEMS structure's inputs. Common-mode rejection is performed by the mechanical transconductor, while the sense loop's crossover frequency sets the signal bandwidth.(cont.) The performance of the amplifier agreed very well with hand calculations and simulations. The noise performance was dominated by the total noise at the preamplifier's input. The noise performance achieved in this design was 55 ... Hz , which is higher than that of other high performance amplifiers. Based on the analytical model created for the amplifier, a noise level of 450 ... Hz can be achieved when the circuitry is fully integrated with the sensor.by Akin Adeniyi Aina.Ph.D

Low power design techniques for analog-to-digital converters in submicron CMOS

Advances in process technologies have led to the development of low-power high speed digital signal processing blocks that occupy small areas. These advances are critical in the development of portable electronic devices with small feature size and long battery life. However, the design of analog and mixed-signal building blocks, especially analog-to-digital converters (ADCs), becomes complex and power-inefficient with each advance in process node. This is because of decreased headroom and low intrinsic gain. In this thesis, circuit techniques that enable the design of low-complexity power-efficient ADCs in submicron CMOS are introduced. The techniques include improved correlated level shifting that allow the use of simple low gain amplifiers to realize high performance pipelined and delta-sigma ADCs. Also included is an investigation of the possibility of replacing the power-hungry amplifier in integrators, used in delta-sigma modulators, with low power zero-crossing-based ones. Simulation results of a correlated level shifting pipelined ADC and measurement results of a fabricated prototype of a zero-crossing-based delta-sigma ADC are employed to discuss the effectiveness of the techniques in achieving compact low-power designs