Survey of DC-DC Non-Isolated Topologies for Unidirectional Power Flow in Fuel Cell Vehicles

The automobile companies are focusing on recent technologies such as growing Hydrogen (H2) and Fuel Cell (FC) Vehicular Power Train (VPT) to improve the Tank-To-Wheel (TTW) efficiency. Benefits, the lower cost, `Eco\u27 friendly, zero-emission and high-power capacity, etc. In the power train of fuel cell vehicles, the DC-DC power converters play a vital role to boost the fuel cell stack voltage. Hence, satisfy the demand of the motor and transmission in the vehicles. Several DC-DC converter topologies have proposed for various vehicular applications like fuel cell, battery, and renewable energy fed hybrid vehicles etc. Most cases, the DC-DC power converters are viable and cost-effective solutions for FC-VPT with reduced size and increased efficiency. This article describes the state-of-the-art in unidirectional non-isolated DC-DC Multistage Power Converter (MPC) topologies for FC-VPT application. The paper presented the comprehensive review, comparison of different topologies and stated the suitability for different vehicular applications. This article also discusses the DC-DC MPC applications more specific to the power train of a small vehicle to large vehicles (bus, trucks etc.). Further, the advantages and disadvantages pointed out with the prominent features for converters. Finally, the classification of the DC-DC converters, its challenges, and applications for FC technology is presented in the review article as state-of-the-art in research

Switched Capacitor Loop Filter 와 Source Switched Charge Pump 를 이용한 Phase-Locked Loop 의 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.This thesis proposes a low integrated RMS jitter and low reference spur phase locked loop (PLL) using a switched capacitor loop filter and source switched charge pump. The PLL employs a single tunable charge pump which reduces current mis match across wide control voltage range and charge sharing effect to get high perfor mance of reference spur level. The switched capacitor loop filter is adopted to achieve insensitivity to temperature, supply voltage, and process variation of a resistor. The proposed PLL covers a wide frequency range and has a low integrated RMS jitter and low reference spur level to target various interface standards. The mechanism of switched capacitor loop filter and source switched charge pump is analyzed. Fabricated in 40 nm CMOS technology, the proposed analog PLL provides four phase for a quarter-rate transmitter, consumes 6.35 mW at 12 GHz using 750 MHz reference clock, and occupies an 0.008 mm2 with an integrated RMS jitter (10 kHz to 100 MHz) of 244.8 fs. As a result, the PLL achieves a figure of merit (FoM) of -244.2 dB with high power efficiency of 0.53 mW/GHz, and reference spur level is -60.3 dBc.본 논문에서는 낮은 RMS jitter 와 낮은 레퍼런스 스퍼를 가지며 스위치축전기 루프 필터와 소스 스위치 전하 펌프를 이용한 PLL 을 제안한다. 제안된 PLL 은 레퍼런스 스퍼의 성능을 위해 넓은 컨트롤 전압의 범위 동안 전류의 오차를 줄여주고 전하 공유 효과를 줄여주는 하나의 조절 가능한 전하 펌프를 사용하였다. 저항의 온도, 공급 전압, 공정 변화에 따른 민감도를 낮추기 위해 스위치 축전기 루프 필터가 사용되었다. 다양한 인터페이스 표준을 지원하기 위해 제안하는 PLL 은 넓은 주파수 범위를 지원하고 낮은 RMS jitter 와 낮은 레퍼런스 스퍼를 갖는다. 스위치 축전기 루프 필터와 소스 스위치 전하 펌프의 동작 원리에 대해 분석하였다. 40 nm CMOS 공정으로 제작되었으며, 제안된 회로는 quarter-rate 송신기를 위해 4 개의 phase 를 만들어내며 750 MHz 의 레퍼런스 클락을 이용하여 12 GHz 에서 6.35 mW 의 power 를 소모하고 0.008mm2 의 유효 면적을 차지하고 10 kHz 부터 100 MHz 까지 적분했을 때의 RMS jitter 값은 244.8fs 이다. 제안하는 PLL 은 -244.2 dB 의 FoM, 0.53 mW/GHz 의 power 효율을 달성했으며 레퍼런스 스퍼는 -60.3 dBc 이다CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUNDS 4 2.1 CLOCK GENERATION IN SERIAL LINK 4 2.2 PLL BUILDING BLOCKS 6 2.2.1 OVERVIEW 6 2.2.2 PHASE FREQUENCY DETECTOR 7 2.2.3 CHARGE PUMP AND LOOP FILTER 9 2.2.4 VOLTAGE CONTROLLED OSCILLATOR 10 2.2.5 FREQUENCY DIVIDER 13 2.3 PLL LOOP ANALYSIS 15 CHAPTER 3 PLL WITH SWITCHED CAPACITOR LOOP FILTER AND SOURCE SWITCHED CHARGE PUMP 19 3.1 DESIGN CONSIDERATION 19 3.2 PROPOSED ARCHITECTURE 21 3.3 CIRCUIT IMPLEMENTATION 23 3.3.1 PHASE FREQUENCY DETECTOR 23 3.3.2 SOURCE SWITCHED CHARGE PUMP 26 3.3.3 SWITCHED CAPACITOR LOOP FILTER 30 3.3.4 VOLTAGE CONTROLLED OSCILLATOR 35 3.3.5 POST VCO AMPLIFIER 39 3.3.6 FREQUENCY DIVIDER 40 CHAPTER 4 MEASUREMENT RESULTS 43 4.1 CHIP PHOTOMICROGRAPH 43 4.2 MEASUREMENT SETUP 45 4.3 MEASURED PHASE NOISE AND REFERENCE SPUR 47 4.4 PERFORMANCE SUMMARY 50 CHAPTER 5 CONCLUSION 52 BIBLIOGRAPHY 53 초 록 58석