Asynchronous designs on FPGA with soft error tolerance for security algorithms

Asynchronous methodologies, such as Null Convention Logic (NCL), have tremendous potential in implementing digital logic. It is essential to design complex asynchronous circuits using commercial Electronic Design Automation (EDA) tools. The main focus of this thesis is to design NCL circuits using VHDL and implementing them on FPGAs. The major contributions of this thesis include: 1) Developing a methodology of designing NCL circuits with VHDL and applying it successfully to all practical designs in this thesis. 2) As an example, the NCL circuit for DES (Data Encryption Standard) algorithm has been designed and simulated using VHDL and the implementation issues on various FPGAs (Xilinx and Altera) have been investigated. Modification of the design has been done to minimize the amount of logic used. 3) An effective soft error tolerant scheme for asynchronous circuits on FPGAs is proposed, and successfully verified through software simulation and hardware implementation by introducing it into a DES round. This thesis provides a starting point for further investigation of NCL circuits, in terms of VHDL modeling, FPGA implementations, and soft error tolerance

Digital PLL for ISM applications

In modern transceivers, a low power PLL is a key block. It is known that with the evolution of technology, lower power and high performance circuitry is a challenging demand. In this thesis, a low power PLL is developed in order not to exceed 2mW of total power consumption. It is composed by small area blocks which is one of the main demands. The blocks that compose the PLL are widely abridged and the final solution is shown, showing why it is employed. The VCO block is a Current-Starved Ring Oscillator with a frequency range from 400MHz to 1.5GHz, with a 300μW to approximately 660μW power consumption. The divider is composed by six TSPC D Flip-Flop in series, forming a divide-by-64 divider. The Phase-Detector is a Dual D Flip-Flop detector with a charge pump. The PLL has less than a 2us lock time and presents a output oscillation of 1GHz, as expected. It also has a total power consumption of 1.3mW, therefore fulfilling all the specifications. The main contributions of this thesis are that this PLL can be applied in ISM applications due to its covering frequency range and low cost 130nm CMOS technology

Efficient verification of VLSI circuits based on syntax and denotational semantics

Also issued as: Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.Includes bibliographical references (p. 139-141).Support provided by Analog Devices.Filip Van Aelten

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

Implementation of 32 Bit Brent Kung Adder Using Complementary Pass Transistor Logic

Adders are the most vital part of any digital system. Providing an efficient adder design which satisfies the tradeoff between speed and space aides in increasing the performance of the system. In the modern age in addition to the tradeoff between speed and space, power consumption plays a vital role. Devices with low power consumption and good performance are always preferred. Parallel Prefix adder are the ones widely used in Digital Design. This is primarily because of the flexibility in designing the Adders. Brent Kung Adder is a low power adder, as it uses minimum circuitry to obtain the result. The use of Complementary Pass transistor Logic aides in increasing the performance of the design by using the multiplexer approach in designing the various cells. The 16 bit design is extended to 32 bit, implemented in the physical level and successfully simulated. The area and delay results are accordingly illustrated.Electrical Engineerin

Can my chip behave like my brain?

Many decades ago, Carver Mead established the foundations of neuromorphic systems. Neuromorphic systems are analog circuits that emulate biology. These circuits utilize subthreshold dynamics of CMOS transistors to mimic the behavior of neurons. The objective is to not only simulate the human brain, but also to build useful applications using these bio-inspired circuits for ultra low power speech processing, image processing, and robotics. This can be achieved using reconfigurable hardware, like field programmable analog arrays (FPAAs), which enable configuring different applications on a cross platform system. As digital systems saturate in terms of power efficiency, this alternate approach has the potential to improve computational efficiency by approximately eight orders of magnitude. These systems, which include analog, digital, and neuromorphic elements combine to result in a very powerful reconfigurable processing machine.Ph.D

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

An Accurate Timing Model for Fault Simulation in MOS Circuits

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySemiconductor Research Corporation / 88-DP-109Joint Services Electronics Program / N00014-84-C-0149U of I OnlyRestricted to UIUC communit

A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. Postlayout simulations indicate that mC2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes