168,911 research outputs found

    Optically reconfigurable 1 x 4 remote node switch for access networks

    Get PDF
    In this paper we demonstrate an optically controlled 1 x 4 remote node switch, based on membrane InP switches bonded to a silicon-on-insulator circuit. We show that the switch exhibits cross talk better than 25 dB between the output ports, and that the switch operates without receiver sensitivity penalty. Furthermore, the proposed switch architecture allows for optical clock distribution as a means to avoid the need for clock recovery at the receiver side. This is demonstrated in a proof-of-principle experiment where data and clock are sent through a single membrane InP switch

    The Octopus switch

    Get PDF
    This chapter1 discusses the interconnection architecture of the Mobile Digital Companion. The approach to build a low-power handheld multimedia computer presented here is to have autonomous, reconfigurable modules such as network, video and audio devices, interconnected by a switch rather than by a bus, and to offload as much as work as possible from the CPU to programmable modules placed in the data streams. Thus, communication between components is not broadcast over a bus but delivered exactly where it is needed, work is carried out where the data passes through, bypassing the memory. The amount of buffering is minimised, and if it is required at all, it is placed right on the data path, where it is needed. A reconfigurable internal communication network switch called Octopus exploits locality of reference and eliminates wasteful data copies. The switch is implemented as a simplified ATM switch and provides Quality of Service guarantees and enough bandwidth for multimedia applications. We have built a testbed of the architecture, of which we will present performance and energy consumption characteristics

    MKAS : A modular knockout ATM switch

    Get PDF
    Simple Knockout Switch [11 exhibits excellent traffic performance (cell loss, cell delay and maximum throughput etc.) under uniform as well as non-uniform traffic patterns (2-6). But being a single stage, its hardware complexity is directly proportional to the switch size N. This problem may bind its implementation for largescale requirements because of the technological and physical constraints of packaging (e. g. chip or board size). Here, we are proposing a two-stage Modular Knockout ATM Switch architecture, which is extendable to large-scale switch sizes without sacrificing any significant decrease in switch performance. The concept of Generalised Knockout Principle in conjunction with Simple Knockout Principle has been utilised to filter, route and resolve the output contention problems in distributed fashion. Using distributed address filtration and shared concentration techniques simplifies the switch functions and reduces the switch complexity to large extent in terms of filters, switching elements and input output interconnection wires

    A Switch Architecture for Real-Time Multimedia Communications

    Get PDF
    In this paper we present a switch that can be used to transfer multimedia type of trafJic. The switch provides a guaranteed throughput and a bounded latency. We focus on the design of a prototype Switching Element using the new technology opportunities being offered today. The architecture meets the multimedia requirements but still has a low complexity and needs a minimum amount of hardware. A main item of this paper will be the background of the architectural design decisions made. These include the interconnection topology, buffer organization, routing and scheduling. The implementation of the switching fabric with FPGAs, allows us to experiment with switching mode, routing strategy and scheduling policy in a multimedia environment. The witching elements are interconnected in a Kautz topology. Kautz graphs have interesting properties such as: a small diametec the degree is independent of the network size, the network is fault-tolerant and has a simple routing algorithm

    Scalable boson-sampling with time-bin encoding using a loop-based architecture

    Full text link
    We present an architecture for arbitrarily scalable boson-sampling using two nested fiber loops. The architecture has fixed experimental complexity, irrespective of the size of the desired interferometer, whose scale is limited only by fiber and switch loss rates. The architecture employs time-bin encoding, whereby the incident photons form a pulse train, which enters the loops. Dynamically controlled loop coupling ratios allow the construction of the arbitrary linear optics interferometers required for boson-sampling. The architecture employs only a single point of interference and may thus be easier to stabilize than other approaches. The scheme has polynomial complexity and could be realized using demonstrated present-day technologies.Comment: 7 pages, 7 figure
    • 

    corecore