Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Novel RF CMOS Integrated Circuits and Systems for Broadband Dielectric Spectroscopy

Broadband dielectric spectroscopy has proven to be a valuable technique for characterization of chemicals and biomaterials. It has the great potential to become an indispensable and cost-effective tool in point-of-care medical applications due to its label-free and non-invasive operation. However, most of the existing dielectric spectroscopy instruments require bulky, heavy and expensive measurement set-up, restricting their use to only special applications in industry and laboratories. Therefore, integrated dielectric spectroscopy on silicon capable of direct detection of chemicals/biomaterials' complex permittivity can yield significant cost and size reduction, system integration, portability, enormous processing, and high throughput. A CMOS wideband dielectric spectroscopy system is proposed for chemical and biological material characterization. The complex permittivity detection is performed using a configurable harmonic-rejecting receiver capable of indirectly measuring the complex admittance of sensing capacitor exposed to the material-under-test (MUT) and subject to RF signal excitation with a frequency range of 0.62-10 GHz. The sensing capacitor is embedded in a voltage divider topology with a fixed capacitor and the relative variations in the magnitude and phase of the voltages across the capacitors are used to find the real and imaginary parts of the permittivity. The sensor achieves an rms permittivity error of less than 1% over the entire operation bandwidth. Using a sub-harmonic mixing scheme, the system can perform complex permittivity measurements from 0.62 to 10 GHz while requiring an input signal source with frequency range of only from 5 to 10 GHz. Thereby, the permittivity measurement system can be easily made self-sustained by implementing a 5-10 GHz frequency synthesizer on the same chip. One of the key building blocks in such a frequency synthesizer is the voltage-controlled oscillator (VCO) which has to cover an octave of frequency range. A novel low-phase-noise wide-tuning range VCO is presented using a triple-band LC resonator. The implemented VCO in 0.18μm CMOS technology achieves a continuous tuning range of 86.7% from 5.12 GHz to 12.95 GHz while drawing 5 to 10 mA current from 1-V supply. The measured phase noise at 1 MHz offset from carrier frequencies of 5.9, 9.12 and 12.25 GHz is -122.9, -117.1 and -110.5 dBc/Hz, respectively. Also, a dual-band quadrature voltage-controlled oscillator (QVCO) is presented using a transformer-based high-order LC-ring resonator which inherently provides quadrature signals without requiring noisy coupling transistors as in traditional approaches. The proposed resonator shows two possible oscillation frequencies which are exploited to realize a wide-tuning range QVCO employing a mode-switching transistor network. Due to the use of transformers, the oscillator has minimal area penalty compared to the conventional designs. The implemented prototype in a 65-nm CMOS process achieves a continuous tuning range of 77.8% from 2.75 GHz to 6.25 GHz while consuming 9.7 to 15.6 mA current from 0.6-V supply. The measured phase noise figure-of-merit (FoM) at 1 MHz offset ranges from 184 dB to 188.2 dB throughout the entire tuning range. The QVCO also exhibits good quadrature accuracy with 1.5º maximum phase error and occupies a relatively small silicon area of 0.35 mm^2

Self-Calibrated, Low-Jitter and Low-Reference-Spur Injection-Locked Clock Multipliers

Department of Electrical EngineeringThis dissertation focuses primarily on the design of calibrators for the injection-locked clock multiplier (ILCM). ILCMs have advantage to achieve an excellent jitter performance at low cost, in terms of area and power consumption. The wide loop bandwidth (BW) of the injection technique could reject the noise of voltage-controlled oscillator (VCO), making it thus suitable for the rejection of poor noise of a ring-VCO and a high frequency LC-VCO. However, it is difficult to use without calibrators because of its sensitiveness in process-voltage-temperature (PVT) variations. In Chapter 2, conventional frequency calibrators are introduced and discussed. This dissertation introduces two types of calibrators for low-power high-frequency LC-VCO-based ILFMs in Chapter 3 and Chapter 4 and high-performance ring-VCO-based ILCM in Chapter 5. First, Chapter 3 presents a low power and compact area LC-tank-based frequency multiplier. In the proposed architecture, the input signals have a pulsed waveform that involves many high-order harmonics. Using an LC-tank that amplifies only the target harmonic component, while suppressing others, the output signal at the target frequency can be obtained. Since the core current flows for a very short duration, due to the pulsed input signals, the average power consumption can be dramatically reduced. Effective removal of spurious tones due to the damping of the signal is achieved using a limiting amplifier. In this work, a prototype frequency tripler using the proposed architecture was designed in a 65 nm CMOS process. The power consumption was 950 ??W, and the active area was 0.08 mm2. At a 3.12 GHz frequency, the phase noise degradation with respect to the theoretical bound was less than 0.5 dB. Second, Chapter 4 presents an ultra-low-phase-noise ILFM for millimeter wave (mm-wave) fifth-generation (5G) transceivers. Using an ultra-low-power frequency-tracking loop (FTL), the proposed ILFM is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion. Since the FTL is monitoring the averages of phase deviations rather than detecting or sampling the instantaneous values, it requires only 600??W to continue to calibrate the ILFM that generates an mm-wave signal with an output frequency from 27 to 30 GHz. The proposed ILFM was fabricated in a 65-nm CMOS process. The 10-MHz phase noise of the 29.25-GHz output signal was ???129.7 dBc/Hz, and its variations across temperatures and supply voltages were less than 2 dB. The integrated phase noise from 1 kHz to 100 MHz and the rms jitter were???39.1 dBc and 86 fs, respectively. Third, Chapter 5 presents a low-jitter, low-reference-spur ring voltage-controlled oscillator (ring VCO)-based ILCM. Since the proposed triple-point frequency/phase/slope calibrator (TP-FPSC) can accurately remove the three root causes of the frequency errors of ILCMs (i.e., frequency drift, phase offset, and slope modulation), the ILCM of this work is able to achieve a low-level reference spur. In addition, the calibrating loop for the frequency drift of the TP-FPSC offers an additional suppression to the in-band phase noise of the output signal. This capability of the TP-FPSC and the naturally wide bandwidth of the injection-locking mechanism allows the ILCM to achieve a very low RMS jitter. The ILCM was fabricated in a 65-nm CMOS technology. The measured reference spur and RMS jitter were ???72 dBc and 140 fs, respectively, both of which are the best among the state-of-the-art ILCMs. The active silicon area was 0.055 mm2, and the power consumption was 11.0 mW.clos

Design of Digital FMCW Chirp Synthesizer PLLs Using Continuous-Time Delta-Sigma Time-to-Digital Converters

Radar applications for driver assistance systems and autonomous vehicles have spurred the development of frequency-modulated continuous-wave (FMCW) radar. Continuous signal transmission and high operation frequencies in the K- and W-bands enable radar systems with low power consumption and small form factors. The radar performance depends on high-quality signal sources for chirp generation to ensure accurate and reliable target detection, requiring chirp synthesizers that offer fast frequency settling and low phase noise. Fractional-N phase locked loops (PLLs) are an effective tool for synthesis of FMCW waveform profiles, and advances in CMOS technology have enabled high-performance single-chip CMOS synthesizers for FMCW radar. Design approaches for FMCW chirp synthesizer PLLs need to address the conflicting requirements of fast settling and low close-in phase noise. While integrated PLLs can be implemented as analog or digital PLLs, analog PLLs still dominate for high frequencies. Digital PLLs offer greater programmability and area efficiency than their analog counterparts, but rely on high-resolution time-to-digital converters (TDCs) for low close-in phase noise. Performance limitations of conventional TDCs remain a roadblock for achieving low phase noise with high-frequency digital PLLs. This shortcoming of digital PLLs becomes even more pronounced with wide loop bandwidths as required for FMCW radar. To address this problem, this work presents digital FMCW chirp synthesizer PLLs using continuous-time delta-sigma TDCs. After a discussion of the requirements for PLL-based FMCW chirp synthesizers, this dissertation focuses on digital fractional-N PLL designs based on noise-shaping TDCs that leverage state-of-the-art delta-sigma modulator techniques to achieve low close-in phase noise in wide-bandwidth digital PLLs. First, an analysis of the PLL bandwidth and chirp linearity studies the design requirements for chirp synthesizer PLLs. Based on a model of a complete radar system, the analysis examines the impact of the PLL bandwidth on the radar performance. The modeling approach allows for a straightforward study of the radar accuracy and reliability as functions of the chirp parameters and the PLL configuration. Next, an 18-to-22GHz chirp synthesizer PLL that produces a 25-segment chirp for a 240GHz FMCW radar application is described. This synthesizer design adapts an existing third-order noise-shaping TDC design. A 65nm CMOS prototype achieves a measured close-in phase noise of -88dBc/Hz at 100kHz offset for wide PLL bandwidths and consumes 39.6mW. The prototype drives a radar testbed to demonstrate the effectiveness of the synthesizer design in a complete radar system. Finally, a second-order noise-shaping TDC based on a fourth-order bandpass delta-sigma modulator is introduced. This bandpass delta-sigma TDC leverages the high resolution of a bandpass delta-sigma modulator by sampling a sinusoidal PLL reference and applies digital down-conversion to achieve low TDC noise in the frequency band of interest. Based on the bandpass delta-sigma TDC, a 38GHz digital FMCW chirp synthesizer PLL is designed. The feedback divider applies phase interpolation with a phase rotation scheme to ensure the effectiveness of the low TDC noise. A prototype PLL, fabricated in 40nm CMOS, achieves a measured close-in phase noise of -85dBc/Hz at 100kHz offset for wide loop bandwidths >1MHz and consumes 68mW. It effectively generates fast (500MHz/55us) and precise (824kHz rms frequency error) triangular chirps for FMCW radar. The bandpass delta-sigma TDC achieves a measured integrated rms noise of 325fs in a 1MHz bandwidth.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147732/1/dweyer_1.pdfDescription of dweyer_1.pdf : Restricted to UM users only

Techniques for high-performance digital frequency synthesis and phase control

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 183-190).This thesis presents a 3.6-GHz, 500-kHz bandwidth digital [delta][sigma] frequency synthesizer architecture that leverages a recently invented noise-shaping time-to-digital converter (TDC) and an all-digital quantization noise cancellation technique to achieve excellent in-band and out-of-band phase noise, respectively. In addition, a passive digital-to-analog converter (DAC) structure is proposed as an efficient interface between the digital loop filter and a conventional hybrid voltage-controlled oscillator (VCO) to create a digitally-controlled oscillator (DCO). An asynchronous divider structure is presented which lowers the required TDC range and avoids the divide-value-dependent delay variation. The prototype is implemented in a 0.13-am CMOS process and its active area occupies 0.95 mm². Operating under 1.5 V, the core parts, excluding the VCO output buffer, dissipate 26 mA. Measured phase noise at 3.67 GHz achieves -108 dBc/Hz and -150 dBc/Hz at 400 kHz and 20 MHz, respectively. Integrated phase noise at this carrier frequency yields 204 fs of jitter (measured from 1 kHz to 40 MHz). In addition, a 3.2-Gb/s delay-locked loop (DLL) in a 0.18-[mu]m CMOS for chip-tochip communications is presented. By leveraging the fractional-N synthesizer technique, this architecture provides a digitally-controlled delay adjustment with a fine resolution and infinite range. The provided delay resolution is less sensitive to the process, voltage, and temperature variations than conventional techniques. A new [delta][sigma] modulator enables a compact and low-power implementation of this architecture. A simple bang-bang detector is used for phase detection. The prototype operates at a 1.8-V supply voltage with a current consumption of 55 mA. The phase resolution and differential rms clock jitter are 1.4 degrees and 3.6 ps, respectively.by Chun-Ming Hsu.Ph.D

Flexible Receivers in CMOS for Wireless Communication

Consumers are pushing for higher data rates to support more services that are introduced in mobile applications. As an example, a few years ago video-on-demand was only accessed through landlines, but today wireless devices are frequently used to stream video. To support this, more flexible network solutions have merged in 4G, introducing new technical problems to the mobile terminal. New techniques are thus needed, and this dissertation explores five different ideas for receiver front-ends, that are cost-efficient and flexible both in performance and operating frequency. All ideas have been implemented in chips fabricated in 65 nm CMOS technology and verified by measurements. Paper I explores a voltage-mode receiver front-end where sub-threshold positive feedback transistors are introduced to increase the linearity in combination with a bootstrapped passive mixer. Paper II builds on the idea of 8-phase harmonic rejection, but simplifies it to a 6-phase solution that can reject noise and interferers at the 3rd order harmonic of the local oscillator frequency. This provides a good trade-off between the traditional quadrature mixer and the 8- phase harmonic rejection mixer. Furthermore, a very compact inductor-less low noise amplifier is introduced. Paper III investigates the use of global negative feedback in a receiver front-end, and also introduces an auxiliary path that can cancel noise from the main path. In paper IV, another global feedback based receiver front-end is designed, but with positive feedback instead of negative. By introducing global positive feedback, the resistance of the transistors in a passive mixer-first receiver front-end can be reduced to achieve a lower noise figure, while still maintaining input matching. Finally, paper V introduces a full receiver chain with a single-ended to differential LNA, current-mode downconversion mixers, and a baseband circuity that merges the functionalities of the transimpedance amplifier, channel-select filter, and analog-to-digital converter into one single power-efficient block

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Innovative Design and Realization of Microwave and Millimeter-Wave Integrated circuits

Ph.DDOCTOR OF PHILOSOPH